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公开(公告)号：US07316975B2
公开(公告)日：2008-01-08
申请号：US11177216
申请日：2005-07-08
申请人： Markus Lenski , Wolfgang Buchholtz , Andy Wei , Michael Raab
发明人： Markus Lenski , Wolfgang Buchholtz , Andy Wei , Michael Raab
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/823468
摘要： A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.
摘要翻译： 提供了包括第一晶体管元件和第二晶体管元件的衬底。 一层材料沉积在第一晶体管元件和第二晶体管元件上。 材料层的一部分被修饰，其可以例如通过用离子照射部分或执行各向同性蚀刻工艺来实现，以减小其厚度。 执行适于比位于第二晶体管元件上方的层的未修改部分更快地去除材料层的修饰部分的蚀刻工艺。
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公开(公告)号：US20060115988A1
公开(公告)日：2006-06-01
申请号：US11177216
申请日：2005-07-08
申请人： Markus Lenski , Wolfgang Buchholtz , Andy Wei , Michael Raab
发明人： Markus Lenski , Wolfgang Buchholtz , Andy Wei , Michael Raab
IPC分类号： H01L21/461
CPC分类号： H01L21/823468
摘要： A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.
摘要翻译： 提供了包括第一晶体管元件和第二晶体管元件的衬底。 一层材料沉积在第一晶体管元件和第二晶体管元件上。 材料层的一部分被修饰，其可以例如通过用离子照射部分或执行各向同性蚀刻工艺来实现，以减小其厚度。 执行适于比位于第二晶体管元件上方的层的未修改部分更快地去除材料层的修饰部分的蚀刻工艺。
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3.发明授权Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy 有权通过在形成应变诱导半导体合金时减小电介质盖层的材料侵蚀，增强了对高K金属栅电极结构的限制公开(公告)号：US08349694B2
公开(公告)日：2013-01-08
申请号：US12909149
申请日：2010-10-21
申请人： Stephan Kronholz , Markus Lenski , Andy Wei , Martin Gerhardt
发明人： Stephan Kronholz , Markus Lenski , Andy Wei , Martin Gerhardt
IPC分类号： H01L21/28 , H01L27/12 , H01L21/8238 , H01L21/84 , H01L29/165 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.
摘要翻译： 当在复杂的半导体器件的一种类型的晶体管中形成应变诱导半导体合金时，可以通过在每个栅极电极结构上形成封装间隔元件并提供额外的硬度来实现栅电极结构的电介质盖材料的优良厚度均匀性 面具材料。 因此，特别地，在复杂的替代栅极方法中，可以在稍后的制造阶段中有效地去除电介质盖材料，从而避免在用电极金属替换半导体材料时的任何不规则性。
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4.发明授权Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors 有权用于增强应力传递到NMOS和PMOS晶体管的沟道区域的技术公开(公告)号：US07344984B2
公开(公告)日：2008-03-18
申请号：US11468450
申请日：2006-08-30
申请人： Jan Hoentschel , Andy Wei , Markus Lenski , Peter Javorka
发明人： Jan Hoentschel , Andy Wei , Markus Lenski , Peter Javorka
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7843
摘要： A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.
摘要翻译： 提供了一种方法和半导体器件，其中具有特定固有应力的各个接触层可以直接形成在各自的金属硅化物区域上，而在用于去除最初沉积的接触层的不希望的部分的蚀刻工艺期间不会有不适当的金属硅化物降解。 此外，由于本发明构思，应变感应接触层可以直接形成在相应的大致L形间隔元件上，从而进一步增强应力传递机构。
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5.发明授权Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions 有权用于监测在漏极/源极区域中形成嵌入式半导体合金的工艺特性的测试结构公开(公告)号：US08227266B2
公开(公告)日：2012-07-24
申请号：US12716472
申请日：2010-03-03
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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6.发明申请ENHANCED CONFINEMENT OF HIGH-K METAL GATE ELECTRODE STRUCTURES BY REDUCING MATERIAL EROSION OF A DIELECTRIC CAP LAYER UPON FORMING A STRAIN-INDUCING SEMICONDUCTOR ALLOY 有权通过减少电介质层的材料腐蚀形成应变诱导半导体合金来增强高K金属电极结构的增强公开(公告)号：US20110159654A1
公开(公告)日：2011-06-30
申请号：US12909149
申请日：2010-10-21
申请人： Stephan Kronholz , Markus Lenski , Andy Wei , Martin Gerhardt
发明人： Stephan Kronholz , Markus Lenski , Andy Wei , Martin Gerhardt
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.
摘要翻译： 当在复杂的半导体器件的一种类型的晶体管中形成应变诱导半导体合金时，可以通过在每个栅极电极结构上形成封装间隔元件并提供额外的硬度来实现栅电极结构的电介质盖材料的优良厚度均匀性 面具材料。 因此，特别地，在复杂的替代栅极方法中，可以在稍后的制造阶段中有效地去除电介质盖材料，从而避免在用电极金属替换半导体材料时的任何不规则性。
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7.发明申请TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION 有权具有嵌入式SI / GE材料的晶体管具有减少偏移到通道区域公开(公告)号：US20100078689A1
公开(公告)日：2010-04-01
申请号：US12552642
申请日：2009-09-02
申请人： Stephan Kronholz , Markus Lenski , Andy Wei , Andreas Ott
发明人： Stephan Kronholz , Markus Lenski , Andy Wei , Andreas Ott
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66636 , H01L29/7848
摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.
摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。
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8.发明申请TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS 有权用于在排水/源区域形成嵌入式半导体合金的监测过程特性的测试结构公开(公告)号：US20090166618A1
公开(公告)日：2009-07-02
申请号：US12132014
申请日：2008-06-03
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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9.发明授权Transistor with embedded Si/Ge material having reduced offset to the channel region 有权具有嵌入的Si / Ge材料的晶体管具有减小到沟道区的偏移公开(公告)号：US08071442B2
公开(公告)日：2011-12-06
申请号：US12552642
申请日：2009-09-02
申请人： Stephan Kronholz , Markus Lenski , Andy Wei , Andreas Ott
发明人： Stephan Kronholz , Markus Lenski , Andy Wei , Andreas Ott
IPC分类号： H01L21/8242
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66636 , H01L29/7848
摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.
摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。
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10.发明申请TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS 有权用于在排水/源区域形成嵌入式半导体合金的监测过程特性的测试结构公开(公告)号：US20100155727A1
公开(公告)日：2010-06-24
申请号：US12716472
申请日：2010-03-03
申请人： ANTHONY MOWRY , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： ANTHONY MOWRY , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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