公开(公告)号：US09699014B2

公开(公告)日：2017-07-04

申请号：US13412533

申请日：2012-03-05

申请人： Markus Schimper ,  Franz Kuttner

发明人： Markus Schimper ,  Franz Kuttner

IPC分类号： H04L27/36

CPC分类号： H04L27/361 ,  H04L27/367

摘要： This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.

公开(公告)号：US08130865B2

公开(公告)日：2012-03-06

申请号：US12262335

申请日：2008-10-31

申请人： Markus Schimper ,  Franz Kuttner

发明人： Markus Schimper ,  Franz Kuttner

IPC分类号： H04L25/49

CPC分类号： H04L27/361 ,  H04L27/367

摘要： In one implementation, a polar transmitter includes a digital signal processing component that processes baseband signals and provides a baseband data signal with amplitude values; and a digital pre-distortion component that receives the baseband data signal with amplitude values, compensates for jitter error in the baseband data signal with amplitude values, and provides an adjusted modulated signal.

摘要翻译： 在一个实现中，极性发射器包括处理基带信号并提供具有振幅值的基带数据信号的数字信号处理部件; 以及以幅度值接收基带数据信号的数字预失真分量，以幅度值补偿基带数据信号中的抖动误差，并提供经调整的调制信号。

公开(公告)号：US20120170673A1

公开(公告)日：2012-07-05

申请号：US13412533

申请日：2012-03-05

申请人： Markus Schimper ,  Franz Kuttner

发明人： Markus Schimper ,  Franz Kuttner

IPC分类号： H04L5/12 ,  H04L25/49

CPC分类号： H04L27/361 ,  H04L27/367

摘要： This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.

摘要翻译： 本公开涉及抑制收发器中极性调制器的数模转换（DAC）电路中调制时钟抖动的影响的技术和方法。 调制器电路中的锁相环（PLL）可能在DAC产生的脉冲中引入确定性抖动，这可能导致DAC产生的脉冲的幅度变化。 时钟抖动可以将输入幅度的占空比改变为DAC，这可能导致DAC产生的脉冲的输出的变化。 可以在DAC电路之前引入数字预失真或数字乘法器电路，以增加或减小DAC幅度以补偿脉宽调制。

公开(公告)号：US20100111222A1

公开(公告)日：2010-05-06

申请号：US12262335

申请日：2008-10-31

申请人： Markus Schimper ,  Franz Kuttner

发明人： Markus Schimper ,  Franz Kuttner

IPC分类号： H04L25/49 ,  H04B1/04

CPC分类号： H04L27/361 ,  H04L27/367

摘要： This disclosure relates to clock jitter suppression in digital to analog converter generated pulses for a polar transmitter.

摘要翻译： 本公开涉及用于极性发射器的数模转换器产生的脉冲中的时钟抖动抑制。

公开(公告)号：US08854127B2

公开(公告)日：2014-10-07

申请号：US13471839

申请日：2012-05-15

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03G3/20

CPC分类号： H02M3/158 ,  H02M3/157 ,  H03F1/0227 ,  H03F1/025

摘要： Embodiments provide a DC-DC converter (DC-DC=direct current to direct current) for envelope tracking. The DC-DC converter includes a digital control stage and a driving stage. The digital control stage is configured to provide a digital control signal based on digital information describing an amplitude of a digital baseband transmit signal. The driving stage is configured to provide a supply voltage for an RF amplifier (RF=radio frequency) based on the digital control signal.

摘要翻译： 实施例提供用于包络跟踪的DC-DC转换器（DC-DC =直流电流）。 DC-DC转换器包括数字控制级和驱动级。 数字控制级被配置为基于描述数字基带发送信号的幅度的数字信息来提供数字控制信号。 驱动级被配置为基于数字控制信号为RF放大器（RF =射频）提供电源电压。

公开(公告)号：US20140146914A1

公开(公告)日：2014-05-29

申请号：US13688980

申请日：2012-11-29

申请人： Franz Kuttner ,  Michael Fulde

发明人： Franz Kuttner ,  Michael Fulde

IPC分类号： H03M1/66 ,  H04L27/04

CPC分类号： H03M1/66 ,  H03M1/0624 ,  H03M1/685

摘要： One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of cells arranged in rows and columns. Each cell includes a current source. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the current sources to an output of the DAC. The number of current sources which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal.

摘要翻译： 本文描述的一个示例涉及数模转换器（DAC）。 DAC包括被配置为接收多位数字输入信号的数字信号输入和以行和列排列的多个单元。 每个单元格包括一个电流源。 行解码器和列解码器向相应的行和相应列提供相应的控制信号，以选择性地将多个电流源耦合到DAC的输出。 通过控制信号耦合到输出的电流源的数量取决于多位数字输入信号。 基于本地振荡器信号调制至少一个控制信号。

公开(公告)号：US08653995B2

公开(公告)日：2014-02-18

申请号：US13103917

申请日：2011-05-09

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03M1/66

CPC分类号： H03M1/1057 ,  H03M1/745

摘要： This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

摘要翻译： 本公开涉及对单端数字模拟电路的当前单元中的电容反馈产生的非线性的补偿。

公开(公告)号：US20070046518A1

公开(公告)日：2007-03-01

申请号：US10564312

申请日：2004-07-07

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03M1/66

CPC分类号： H03M1/066 ,  H03M1/685 ,  H03M3/502

摘要： The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the digital input data (11) on the basis of a predetermined algorithm to determine an initial cell and a final cell in the array arrangement (22), between which there are situated cells (24) with energy sources (30) to be activated; a decoder device (16) for decoding the at least two digital output data items (13, 14) from the DEM device (10) into actuation signals (17, 17′, 18, 18′, 19, 19′ 20, 20′, 21, 21′) in order to activate the cells (24) which are to be activated; and an array arrangement (22) of cells (23) for outputting at least one quantized analog signal (25, 25′) on the basis of the actuation signals (17, 17′, 18, 18′, 19, 19′ 20, 20′, 21, 21′). The present invention likewise provides a method for digital-analog conversion.

公开(公告)号：US06803870B2

公开(公告)日：2004-10-12

申请号：US10642730

申请日：2003-08-19

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03M112

CPC分类号： H03M3/39 ,  H03M3/424 ,  H03M3/426 ,  H03M3/436

摘要： During A/D conversion of time-discrete analog input values, a quantizer is used in which an analog quantization error is obtained after every conversion. The quantization error is stored in a buffer, and fed back through a subtracter to at least one input value of a subsequent conversion. The quantizer has a conversion frequency, which is more than double the maximum frequency contained in input values, so the conversion operates in an oversampling mode. During feedback the quantization errors of several conversions, prior to a varying number of conversions, are preferably fed back to an input value. The invention can be used with all conventional quantizers, for which an analog quantization error can be obtained, so it is possible through a noise shaping procedure to shift quantization noise into higher-frequency spectral ranges to improve the signal-to-noise ratio or reduce the quantization noise in a useful spectral range.

摘要翻译： 在时间离散模拟输入值的A / D转换期间，使用量化器，其中在每次转换之后获得模拟量化误差。 量化误差被存储在缓冲器中，并通过减法器反馈到后续转换的至少一个输入值。 量化器具有转换频率，其大小是输入值中包含的最大频率的两倍，因此转换工作在过采样模式。 在反馈期间，在不同数目的转换之前的几个转换的量化误差优选地被反馈到输入值。 本发明可以与可以获得模拟量化误差的所有常规量化器一起使用，因此可以通过噪声整形过程将量化噪声转换为更高频率的频谱范围来提高信噪比或减小 在有用的光谱范围内的量化噪声。

公开(公告)号：US06181215B2

公开(公告)日：2001-01-30

申请号：US09519542

申请日：2000-03-06

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03B536

CPC分类号： H03B5/366 ,  H03J2200/10 ,  H03K3/0307 ,  H03L7/0991

摘要： The oscillator circuit has a first and a second circuit node and a parallel circuit of a quartz resonator, a first inverter, and a first resistor element connected between the circuit nodes. The first circuit node is connected to a reference potential via a first capacitor circuit, and the second circuit node is connected to the reference potential via a second capacitor circuit. The first capacitor circuit has at least two capacitors whose first electrode is connected to the reference potential, and whose second electrode is connected to the first circuit node via one switching element each. Furthermore, the oscillator circuit has a precharging circuit for precharging the capacitors, and a synchronizing circuit for switching in the capacitors at an instant in which the precharging potential corresponds to the potential at the first circuit node.

摘要翻译： 振荡器电路具有连接在电路节点之间的第一和第二电路节点和石英谐振器，第一反相器和第一电阻元件的并联电路。 第一电路节点通过第一电容器电路连接到参考电位，并且第二电路节点经由第二电容器电路连接到参考电位。 第一电容器电路具有至少两个电容器，其第一电极连接到参考电位，并且其第二电极通过一个开关元件连接到第一电路节点。 此外，振荡器电路具有用于对电容器进行预充电的预充电电路，以及用于在预充电电位对应于第一电路节点处的电位的瞬间切换电容器的同步电路。