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    Method for calibrating a digital/analog converter and digital/analog converter
    1.
    发明授权
    Method for calibrating a digital/analog converter and digital/analog converter 有权
    校准数字/模拟转换器和数/模转换器的方法

    公开(公告)号：US07372383B2

    公开(公告)日：2008-05-13

    申请号：US11403470

    申请日：2006-04-13

    申请人： Martin Clara ,  Antonio Di Giandomenico ,  Wolfgang Klatzer ,  Luca Gori

    发明人： Martin Clara ,  Antonio Di Giandomenico ,  Wolfgang Klatzer ,  Luca Gori

    IPC分类号： H03M3/00

    CPC分类号： H03M1/0614 ,  H03M1/1057 ,  H03M1/74

    摘要： A digital/analog converter comprises a converter array comprised of a plurality of converter cells and a device for self-calibration of the converter cells. The device for self-calibration comprises at least one reference cell with a reference value and a control device for controlling a calibration process. The control device calibrates successively, within a respective calibration period, respective of the converter cells to values corresponding to the reference value and adjusts respective calibration periods for a calibration cycle, within which the converter cells are to be calibrated. At least two different of the respective calibration periods differ within at least two calibration cycles.

    摘要翻译： 数字/模拟转换器包括由多个转换器单元组成的转换器阵列和用于转换器单元的自校准的装置。 用于自校准的装置包括具有参考值的至少一个参考单元和用于控制校准过程的控制装置。 控制装置在相应的校准周期内将转换器单元的各个相应地校准到对应于参考值的值，并且调整校准周期的相应校准周期，在校准周期内，转换器单元将被校准。 至少两个校准周期中至少两个不同的校准周期在至少两个校准周期内不同。

    Method for calibrating a digital/analog converter and digital/analog converter
    4.
    发明申请
    Method for calibrating a digital/analog converter and digital/analog converter 有权
    校准数字/模拟转换器和数/模转换器的方法

    公开(公告)号：US20060232455A1

    公开(公告)日：2006-10-19

    申请号：US11403470

    申请日：2006-04-13

    申请人： Martin Clara ,  Antonio Di Giandomenico ,  Wolfgang Klatzer ,  Luca Gori

    发明人： Martin Clara ,  Antonio Di Giandomenico ,  Wolfgang Klatzer ,  Luca Gori

    IPC分类号： H03M1/10

    CPC分类号： H03M1/0614 ,  H03M1/1057 ,  H03M1/74

    摘要： A digital/analog converter comprises a converter array comprised of a plurality of converter cells and a device for self-calibration of the converter cells. The device for self-calibration comprises at least one reference cell with a reference value and a control device for controlling a calibration process. The control device calibrates successively, within a respective calibration period, respective of the converter cells to values corresponding to the reference value and adjusts respective calibration periods for a calibration cycle, within which the converter cells are to be calibrated. At least two different of the respective calibration periods differ within at least two calibration cycles.

    摘要翻译： 数字/模拟转换器包括由多个转换器单元组成的转换器阵列和用于转换器单元的自校准的装置。 用于自校准的装置包括具有参考值的至少一个参考单元和用于控制校准过程的控制装置。 控制装置在相应的校准周期内将转换器单元的各个相应地校准到对应于参考值的值，并且调整校准周期的相应校准周期，在校准周期内，转换器单元将被校准。 至少两个校准周期中至少两个不同的校准周期在至少两个校准周期内不同。

    Sigma-delta analog-digital converter for an xDSL multistandard input stage
    7.
    发明授权
    Sigma-delta analog-digital converter for an xDSL multistandard input stage 失效
    用于xDSL多标准输入级的Sigma-delta模数转换器

    公开(公告)号：US07576670B2

    公开(公告)日：2009-08-18

    申请号：US11661627

    申请日：2004-09-02

    申请人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

    发明人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

    IPC分类号： H03M3/00

    CPC分类号： H03M3/394 ,  H03M3/406 ,  H03M3/424 ,  H03M3/452

    摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.

    摘要翻译： 本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b） 其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1） 以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号 。

    Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage
    10.
    发明申请
    Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage 失效
    用于Xdsl多标准输入级的Sigma-Delta模拟数字转换器

    公开(公告)号：US20080297385A1

    公开(公告)日：2008-12-04

    申请号：US11661627

    申请日：2004-09-02

    申请人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

    发明人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

    IPC分类号： H03M3/04

    CPC分类号： H03M3/394 ,  H03M3/406 ,  H03M3/424 ,  H03M3/452

    摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.

    摘要翻译： 本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b） 其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1） 以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号 。