公开(公告)号：US09709625B2

公开(公告)日：2017-07-18

申请号：US13170512

申请日：2011-06-28

申请人： Martin Eckert ,  Roland Frech ,  Claudio Siviero ,  Jochen Supper ,  Otto A. Torreiter ,  Thomas-Michael Winkel

发明人： Martin Eckert ,  Roland Frech ,  Claudio Siviero ,  Jochen Supper ,  Otto A. Torreiter ,  Thomas-Michael Winkel

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3185

CPC分类号： G01R31/2851 ,  G01R31/2879 ,  G01R31/3004 ,  G01R31/3012 ,  G01R31/318575

摘要： A method for determining power consumption of a power domain within an integrated circuit is presented. In a first step, a local power supply impedance profile (Z(f)) of this power domain is determined. Subsequently, a local time-resolved power supply voltage (U(t)) is measured while a well-defined periodic activity is executed in power domain. A set of time-domain measured voltage data (U(t)) is thus accumulated and transformed into the frequency domain to yield a voltage spectrum (U(f)). A current spectrum I(t) is calculated from this voltage profile (U(f)) by using the power supply impedance profile Z(f) of this power domain as I(t)=Ff−1{U(f)/Z(f)}. Finally, a time-resolved power consumption spectrum P(t) is determined from measured voltage spectrum U(t)) and calculated current spectrum (I(t)). This power consumption (P(t)) may be compared with a reference (Pref(t)) to verify whether power consumption within power domain matches expectations.

公开(公告)号：US20120013356A1

公开(公告)日：2012-01-19

申请号：US13087550

申请日：2011-04-15

申请人： Martin Eckert ,  Roland Frech ,  Jochen Supper ,  Otto A. Torreiter

发明人： Martin Eckert ,  Roland Frech ,  Jochen Supper ,  Otto A. Torreiter

IPC分类号： G01R31/3187

CPC分类号： G01R31/31721 ,  G01R31/3004

摘要： A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U0(f)) to verify whether power supply quality at the chip location under test is adequate. Alternatively, a local impedance profile Z(f) evaluated from the local voltage profile (U(f)) may be compared to a reference impedance profile Z0(f).

摘要翻译： 一种用于对电子系统内的集成电路芯片进行电源质量自检的方法和系统。 电子系统受到明确的重复活动，例如通过使用调幅系统时钟树。 由于重复的活动导致芯片内的电流消耗，对于芯片上的位置测量时域本地电源电压（U（t））。 一组时域测量电压数据（U（t））被积累并变换到频域以产生局部电压分布（U（f））。 将本地电压曲线（U（f））与参考电压曲线（U0（f））进行比较，以验证被测芯片位置的电源质量是否足够。 或者，可以将从局部电压分布（U（f））估计的局部阻抗曲线Z（f）与参考阻抗曲线Z0（f）进行比较。

公开(公告)号：US08659310B2

公开(公告)日：2014-02-25

申请号：US13087550

申请日：2011-04-15

申请人： Martin Eckert ,  Roland Frech ,  Jochen Supper ,  Otto A. Torreiter

发明人： Martin Eckert ,  Roland Frech ,  Jochen Supper ,  Otto A. Torreiter

IPC分类号： G01R31/3187

CPC分类号： G01R31/31721 ,  G01R31/3004

摘要： A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U0(f)) to verify whether power supply quality at the chip location under test is adequate. Alternatively, a local impedance profile Z(f) evaluated from the local voltage profile (U(f)) may be compared to a reference impedance profile Z0(f).

摘要翻译： 一种用于对电子系统内的集成电路芯片进行电源质量自检的方法和系统。 电子系统受到明确的重复活动，例如通过使用调幅系统时钟树。 由于重复的活动导致芯片内的电流消耗，对于芯片上的位置测量时域本地电源电压（U（t））。 一组时域测量电压数据（U（t））被积累并变换到频域以产生局部电压分布（U（f））。 将本地电压曲线（U（f））与参考电压曲线（U0（f））进行比较，以验证被测芯片位置的电源质量是否足够。 或者，可以将从局部电压分布（U（f））估计的局部阻抗曲线Z（f）与参考阻抗曲线Z0（f）进行比较。

公开(公告)号：US08866504B2

公开(公告)日：2014-10-21

申请号：US13280626

申请日：2011-10-25

申请人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

发明人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R31/3187 ,  G01R31/317

CPC分类号： G01R31/3187 ,  G01R31/31703

摘要： A system for measuring a test voltage level (Vx) in a location within a chip is presented. The system includes an on-chip measurement device with an on-chip comparator and an on-chip storage. The on-chip comparator is configured for comparing the test voltage (Vx) to be measured to a reference voltage (Vref), while the on-chip storage is configured for storing the result of this comparison. The system also includes external (off-chip) equipment for generating the reference voltage (Vref), for generating probe signals for probing the state of the storage and for retrieving the state of said on-chip storage.

摘要翻译： 提出了一种用于测量芯片内部位置的测试电压电平（Vx）的系统。 该系统包括具有片上比较器和片上存储器的片上测量装置。 片上比较器被配置为将待测量的测试电压（Vx）与参考电压（Vref）进行比较，而片上存储被配置用于存储该比较的结果。 该系统还包括用于产生参考电压（Vref）的外部（片外）设备，用于产生用于探测存储器的状态并检索所述片上存储器的状态的探测信号。

公开(公告)号：US20120146674A1

公开(公告)日：2012-06-14

申请号：US13280626

申请日：2011-10-25

申请人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

发明人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R31/3187

CPC分类号： G01R31/3187 ,  G01R31/31703

摘要： A system for measuring a test voltage level (Vx) in a location within a chip is presented. The system includes an on-chip measurement device with an on-chip comparator and an on-chip storage. The on-chip comparator is configured for comparing the test voltage (Vx) to be measured to a reference voltage (Vref), while the on-chip storage is configured for storing the result of this comparison. The system also includes external (off-chip) equipment for generating the reference voltage (Vref), for generating probe signals for probing the state of the storage and for retrieving the state of said on-chip storage.

摘要翻译： 提出了一种用于测量芯片内部位置的测试电压电平（Vx）的系统。 该系统包括具有片上比较器和片上存储器的片上测量装置。 片上比较器被配置为将待测量的测试电压（Vx）与参考电压（Vref）进行比较，而片上存储被配置用于存储该比较的结果。 该系统还包括用于产生参考电压（Vref）的外部（片外）设备，用于产生用于探测存储器的状态并检索所述片上存储器的状态的探测信号。

公开(公告)号：US08535956B2

公开(公告)日：2013-09-17

申请号：US13396207

申请日：2012-02-14

申请人： Martin Eckert ,  Otto Torreiter ,  Quintino L. Trianni

发明人： Martin Eckert ,  Otto Torreiter ,  Quintino L. Trianni

IPC分类号： G01R31/26

CPC分类号： H01L24/75 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/4853 ,  H01L21/67144 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75315 ,  H01L2224/75316 ,  H01L2224/75501 ,  H01L2224/757 ,  H01L2224/75754 ,  H01L2224/75756 ,  H01L2224/759 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81908 ,  H05K13/0413 ,  Y10T29/53178 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

摘要： A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.

摘要翻译： 芯片连接框架用于将集成电路芯片的引脚与芯片载体上的焊盘对齐。 框架块具有限定形成参考角的两个对齐边缘的套筒。 芯片下降到插座中，芯片载体倾斜，同时支撑框架块和芯片，直到芯片在重力作用下移动到参考角。 一旦位于参考角处，通过在x和y方向上移动框架块来仔细调整芯片位置，直到引脚与焊盘对准。 框架块被弹簧偏压以防止在x和y方向上移动，并且使用指旋螺钉来调节框架块的位置。 一旦引脚与焊盘对准，就可以使用柱塞机构来固定集成电路芯片与芯片载体的强制接合。

公开(公告)号：US20120169485A1

公开(公告)日：2012-07-05

申请号：US13337199

申请日：2011-12-26

申请人： Martin Eckert

发明人： Martin Eckert

IPC分类号： G08C19/12

CPC分类号： B25B21/00 ,  B25B23/14 ,  B25F5/00

摘要： An industrial and electrically driven tool includes two mutually independent radio modules so that a redundant communication link to a controller can be set up.

摘要翻译： 工业和电动工具包括两个相互独立的无线电模块，使得可以建立到控制器的冗余通信链路。

公开(公告)号：US08180142B2

公开(公告)日：2012-05-15

申请号：US12326166

申请日：2008-12-02

申请人： Martin Eckert ,  Georg Goecke ,  Marta Junginger ,  Klaus Kempter ,  Markus Ulbricht

发明人： Martin Eckert ,  Georg Goecke ,  Marta Junginger ,  Klaus Kempter ,  Markus Ulbricht

IPC分类号： G06K9/03

CPC分类号： G06T7/001 ,  G06T2207/30148

摘要： Compact graphical representations of common test fail signatures and process related test fails are provided through methods of selecting, calculating and/or presenting information. The input may be a list of failing tests on a sample of devices under test from chip and/or wafer process fails. The failing tests are identified and then other tests that fail at the same time may be identified. Several graphical outputs are provided, including all possible combinations between test fails and between test fails and process fails. The dependencies are printed as sorted two dimensional bitmaps that are compact representations of the results using color codes. Subtraction of two independent bitmaps is provided, which eliminates common properties and emphasizes differences between multiple bitmaps which allows for quick identification of differences of process fails potentially different between the two different bitmaps indicating potential root causes for the selected one of the test fails.

摘要翻译： 通过选择，计算和/或呈现信息的方法提供常见测试失败签名和过程相关测试失败的紧凑图形表示。 输入可以是从芯片和/或晶片处理失败的被测器件的样本的失败测试的列表。 确定失败的测试，然后可以确定同时失败的其他测试。 提供了几个图形输出，包括测试失败和测试失败和进程失败之间的所有可能的组合。 依赖关系作为排序的二维位图打印，这些位图是使用颜色代码的结果的紧凑表示。 提供了两个独立位图的减法，这消除了通用属性，并且强调了多个位图之间的差异，这允许快速识别两个不同位图之间的差异的过程失败，这两个不同的位图表示所选择的一个测试失败的潜在根本原因。

公开(公告)号：US08126703B2

公开(公告)日：2012-02-28

申请号：US12374666

申请日：2007-07-18

申请人： Fred Runge ,  Klaus-Dieter Liedtke ,  Detlef Hardt ,  Martin Eckert ,  Wiebke Johannsen ,  Roman Englert

发明人： Fred Runge ,  Klaus-Dieter Liedtke ,  Detlef Hardt ,  Martin Eckert ,  Wiebke Johannsen ,  Roman Englert

IPC分类号： G06F17/20

CPC分类号： H04M3/493 ,  G06F17/289 ,  G10L15/22 ,  H04M2203/2061

摘要： A method for providing multilingual speech output in an automated spoken dialog system includes setting up a connection between a telecommunications terminal device and the spoken dialog system. In response to a connection setup, a multilingual speech output is provided that includes an output of a first speech sequence in a first language and at least one second speech sequence in at least one second language different from the first language. The first speech sequence and the at least one second speech sequence are output, at least in part, simultaneously.

摘要翻译： 一种用于在自动语音对话系统中提供多语言语音输出的方法包括建立电信终端设备和口语对话系统之间的连接。 响应于连接设置，提供多语言语音输出，其包括第一语言的第一语音序列的输出和不同于第一语言的至少一种第二语言的至少一个第二语音序列。 第一语音序列和至少一个第二语音序列至少部分地同时输出。

公开(公告)号：US20080162146A1

公开(公告)日：2008-07-03

申请号：US11949341

申请日：2007-12-03

申请人： Martin Eckert ,  Roman Englert ,  Wiebke Johannsen ,  Fred Runge ,  Markus Van Ballegooy

发明人： Martin Eckert ,  Roman Englert ,  Wiebke Johannsen ,  Fred Runge ,  Markus Van Ballegooy

IPC分类号： G10L11/00

CPC分类号： G10L15/22 ,  G10L15/005

摘要： A method and device are provided for classifying at least two languages in an automatic dialogue system, which processes digitized speech input. At least one speech recognition method and at least one language identification method are used on the digitized speech input in order, by logical evaluation of the results of the method, to identify the language of the speech input.

摘要翻译： 提供了一种用于在自动对话系统中分类至少两种语言的方法和装置，其处理数字化语音输入。 在数字化语音输入中依次使用至少一种语音识别方法和至少一种语言识别方法，通过逻辑评估方法的结果来识别语音输入的语言。