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1.发明申请Replacement spacers for mosfet fringe capacatance reduction and processes of making same 有权用于mosfet边缘电容减少的替换间隔件和制造它们的过程公开(公告)号：US20100025775A1
公开(公告)日：2010-02-04
申请号：US12220985
申请日：2008-07-30
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/7682 , H01L23/485 , H01L23/5222 , H01L29/4966 , H01L29/66795 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.
摘要翻译： 一种方法包括平面化包括栅叠层和相邻沟槽触点的微电子器件。 该工艺还包括在栅极堆叠处移除栅极间隔物并用导电栅叠层和相邻的嵌入沟槽接触之间的重叠电容降低的电介质取代栅极间隔物。
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2.发明授权Replacement spacers for MOSFET fringe capacitance reduction and processes of making same 有权用于MOSFET边缘电容降低的替代间隔物及其制造方法公开(公告)号：US07838373B2
公开(公告)日：2010-11-23
申请号：US12220985
申请日：2008-07-30
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/7682 , H01L23/485 , H01L23/5222 , H01L29/4966 , H01L29/66795 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.
摘要翻译： 一种方法包括平面化包括栅叠层和相邻沟槽触点的微电子器件。 该工艺还包括在栅极堆叠处移除栅极间隔物并用导电栅叠层和相邻的嵌入沟槽接触之间的重叠电容降低的电介质取代栅极间隔物。
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3.发明申请Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress 有权使用单轴压应力和双轴压应力的互补金属氧化物半导体集成电路公开(公告)号：US20060205167A1
公开(公告)日：2006-09-14
申请号：US11078267
申请日：2005-03-11
申请人： Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Suman Datta , Brian Doyle , Robert Chau , Everett Wang , Philippe Matagne , Lucian Shifren , Been Jin , Mark Stettler , Martin Giles
发明人： Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Suman Datta , Brian Doyle , Robert Chau , Everett Wang , Philippe Matagne , Lucian Shifren , Been Jin , Mark Stettler , Martin Giles
IPC分类号： H01L21/336 , H01L21/44 , H01L21/8234
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/41783 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S438/933
摘要： A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
摘要翻译： 晶体管可以由不同层的硅锗形成，具有梯度锗浓度的最低层和具有恒定锗浓度的上层，使得最底层具有Si 1-x Ge Ge > x 。 在PMOS侧，最高层可以是Si 1-y N y O y的形式。 源极和漏极可以由PMOS侧的Si 1-z N z z z的外延硅锗形成。 在一些实施例中，在PMOS器件中，x大于y且z大于x。 因此，PMOS器件可以在通道方向上具有单轴压应力和面内双轴压应力。 在某些情况下，应力的这种组合可能导致较高的移动性和增加的设备性能。
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公开(公告)号：US20130143385A1
公开(公告)日：2013-06-06
申请号：US13750393
申请日：2013-01-25
IPC分类号： H01L21/8234
CPC分类号： H01L29/7845 , H01L21/8234 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/495 , H01L29/66795 , H01L29/7831 , H01L29/785
摘要： Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
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公开(公告)号：US20140239400A1
公开(公告)日：2014-08-28
申请号：US14273377
申请日：2014-05-08
CPC分类号： H01L29/7845 , H01L21/8234 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/495 , H01L29/66795 , H01L29/7831 , H01L29/785
摘要： Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
摘要翻译： 实施例涉及具有栅极金属填充物的改进的三栅极器件，在三栅极晶体管的至少一部分上提供压缩或拉伸应力，由此增加载流子迁移率和工作频率。 实施例还考虑了使用改进的三栅极器件的方法。
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公开(公告)号：US08362566B2
公开(公告)日：2013-01-29
申请号：US12144469
申请日：2008-06-23
IPC分类号： H01L21/70
CPC分类号： H01L29/7845 , H01L21/8234 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/495 , H01L29/66795 , H01L29/7831 , H01L29/785
摘要： Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
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公开(公告)号：US09224754B2
公开(公告)日：2015-12-29
申请号：US14273377
申请日：2014-05-08
IPC分类号： H01L21/70 , H01L27/12 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/7845 , H01L21/8234 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/495 , H01L29/66795 , H01L29/7831 , H01L29/785
摘要： Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
摘要翻译： 实施例涉及具有栅极金属填充物的改进的三栅极器件，在三栅极晶体管的至少一部分上提供压缩或拉伸应力，由此增加载流子迁移率和工作频率。 实施例还考虑了使用改进的三栅极器件的方法。
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公开(公告)号：US08741733B2
公开(公告)日：2014-06-03
申请号：US13750393
申请日：2013-01-25
IPC分类号： H01L21/76
CPC分类号： H01L29/7845 , H01L21/8234 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/495 , H01L29/66795 , H01L29/7831 , H01L29/785
摘要： Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
摘要翻译： 实施例涉及具有栅极金属填充物的改进的三栅极器件，在三栅极晶体管的至少一部分上提供压缩或拉伸应力，由此增加载流子迁移率和工作频率。 实施例还考虑了使用改进的三栅极器件的方法。
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公开(公告)号：US20090315114A1
公开(公告)日：2009-12-24
申请号：US12144469
申请日：2008-06-23
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L29/7845 , H01L21/8234 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/495 , H01L29/66795 , H01L29/7831 , H01L29/785
摘要： Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
摘要翻译： 实施例涉及具有栅极金属填充物的改进的三栅极器件，在三栅极晶体管的至少一部分上提供压缩或拉伸应力，由此增加载流子迁移率和工作频率。 实施例还考虑了使用改进的三栅极器件的方法。
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10.发明申请公开(公告)号：US20090315120A1
公开(公告)日：2009-12-24
申请号：US12145296
申请日：2008-06-24
申请人： Lucian Shifren , Keith Zawadzki , Martin Giles , Cory Weber
发明人： Lucian Shifren , Keith Zawadzki , Martin Giles , Cory Weber
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L29/66628
摘要： An apparatus comprising a semiconductor substrate; a conductively doped source or drain (source/drain) region at the surface of the substrate; a raised semiconductor layer deposited over the source/drain region to form a raised source/drain region; a via formed in the raised source/drain region having substantially vertical sidewalls reaching partly or substantially to the source/drain region; and a metal contact filling the via.
摘要翻译： 一种包括半导体衬底的装置; 在衬底的表面处的导电掺杂源极或漏极（源极/漏极）区域; 沉积在源极/漏极区域上以形成升高的源极/漏极区域的凸起的半导体层; 在凸起的源极/漏极区域中形成的通孔具有基本上垂直的侧壁，部分地或基本上相对于源极/漏极区域; 以及填充通孔的金属接触件。
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