Field effect transistor and method for the production thereof
    1.
    发明申请
    Field effect transistor and method for the production thereof 审中-公开
    场效应晶体管及其制造方法

    公开(公告)号:US20060231918A1

    公开(公告)日:2006-10-19

    申请号:US10482328

    申请日:2002-06-19

    IPC分类号: H01L29/00

    摘要: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

    摘要翻译: 提供了一种晶体管,其有利地利用了在常规晶体管中提供用于晶体管之间的隔离的区域的一部分。 在这种情况下,可以以自对准的方式扩大通道宽度,而不会出现短路的风险。 根据本发明的场效应晶体管的优点在于,与先前使用的传统晶体管结构相比,可以确保正向电流ION的有效沟道宽度的显着增加,而不必接受集成密度的降低 可以实现。 因此,作为示例,正向电流I ON ON可以增加高达50%,而不必改变有源区域或沟槽隔离的布置。

    Field effect transistor and method for fabricating it
    2.
    发明申请
    Field effect transistor and method for fabricating it 审中-公开
    场效应晶体管及其制造方法

    公开(公告)号:US20060231874A1

    公开(公告)日:2006-10-19

    申请号:US11294380

    申请日:2005-12-06

    摘要: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

    摘要翻译: 提供了一种晶体管,其有利地利用了在常规晶体管中提供用于晶体管之间的隔离的区域的一部分。 在这种情况下,可以以自对准的方式扩大通道宽度,而不会出现短路的风险。 根据本发明的场效应晶体管的优点在于,与先前使用的常规晶体管结构相比,可以确保正向电流I ON ON的有效沟道宽度的显着增加,而没有 以接受可以实现的积分密度的降低。 因此,作为示例,正向电流I ON ON可以增加高达50%,而不必改变有源区域或沟槽隔离的布置。

    Method for producing an electrically conductive contact
    3.
    发明申请
    Method for producing an electrically conductive contact 失效
    用于制造导电触头的方法

    公开(公告)号:US20050079702A1

    公开(公告)日:2005-04-14

    申请号:US10893561

    申请日:2004-07-16

    摘要: An electrically conductive contact can be used to connect an integrated component to an interconnect. A sacrificial layer is deposited on a liner and planarized until a surface of the integrated component is uncovered. The sacrificial layer is patterned to define the later contacts. The layer is covered in a partial region above contact connection regions. An interlevel insulator is deposited and patterned, so that the sacrificial layer can then be stripped out from the partial region. After the removal of the liner, a conductive layer is deposited into the cavity formed as a result of the stripping-out process on the uncovered contact connection regions and optionally into trenches formed at the outset within the interlevel insulator.

    摘要翻译: 可以使用导电触点将集成部件连接到互连。 将牺牲层沉积在衬垫上并且平坦化,直到集成组件的表面未被覆盖。 将牺牲层图案化以限定稍后的接触。 该层被覆盖在接触连接区域上方的局部区域中。 沉积和图案化层间绝缘体,从而可以从部分区域剥离牺牲层。 在去除衬套之后,导电层沉积到由未剥离的接触连接区域上的剥离过程形成的空腔中,并且任选地沉积在层间绝缘体内的开始形成的沟槽中。

    Memory chip with low-temperature layers in the trench capacitor
    4.
    发明申请
    Memory chip with low-temperature layers in the trench capacitor 审中-公开
    内存芯片具有低温层的沟槽电容

    公开(公告)号:US20050090053A1

    公开(公告)日:2005-04-28

    申请号:US10501880

    申请日:2003-01-08

    IPC分类号: H01L21/8242 H01L27/108

    摘要: Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.

    摘要翻译: 具有沟槽电容器的存储单元,沟槽电容器至少部分地填充有不能承受在制造存储器芯片期间使用的高温处理而不损害其电参数的材料。 本发明的重要内容是在高温处理之后将沟槽电容器的材料引入沟槽。 根据本发明的方法使得可以使用具有大介电常数的电介质层和由金属材料制成的电极层。 与已知的沟槽电容器相比,沟槽电容器的电性能得到改善。

    Field effect transistor and method for fabricating it
    5.
    发明授权
    Field effect transistor and method for fabricating it 有权
    场效应晶体管及其制造方法

    公开(公告)号:US07119384B2

    公开(公告)日:2006-10-10

    申请号:US10482331

    申请日:2002-06-25

    摘要: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

    摘要翻译: 本发明涉及一种场效应晶体管,其中,通过在该高度的侧面上的另外的垂直沟道区,在该高度的上表面上的平面通道区域的宽度被延伸。 所述另外的垂直通道区域直接连接到平面通道区域(垂直扩展通道区域)。 所述场效应晶体管的优点在于,相对于直到现在使用的常规晶体管结构,可以保证电流I ON的有效沟道宽度的显着增加,而不必接受 可实现的集成密度。 所述场效应晶体管还具有低反向电流I OFF。 实现上述优点,而不必使栅极绝缘体的厚度直到电荷转移隧道的区域必须减小或稳定性降低。

    Field effect transistor and method for production thereof
    6.
    发明申请
    Field effect transistor and method for production thereof 有权
    场效应晶体管及其制造方法

    公开(公告)号:US20050029583A1

    公开(公告)日:2005-02-10

    申请号:US10482331

    申请日:2002-06-25

    摘要: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

    摘要翻译: 本发明涉及一种场效应晶体管,其中,通过在该高度的侧面上的另外的垂直沟道区,在该高度的上表面上的平面通道区域的宽度被延伸。 所述另外的垂直通道区域直接连接到平面通道区域(垂直扩展通道区域)。 所述场效应晶体管的优点在于,相对于直到现在使用的常规晶体管结构,可以保证电流ION的有效沟道宽度的显着增加,而不必接受可实现的积分密度的降低。 所述场效应晶体管还具有低反向电流IOFF。 实现上述优点,而不必使栅极绝缘体的厚度直到电荷转移隧道的区域必须减小或稳定性降低。

    Memory chip having a memory cell with low-temperature layers in the memory trench and fabrication method
    7.
    发明申请
    Memory chip having a memory cell with low-temperature layers in the memory trench and fabrication method 审中-公开
    存储芯片具有存储槽中具有低温层的存储单元和制造方法

    公开(公告)号:US20070134871A1

    公开(公告)日:2007-06-14

    申请号:US11702162

    申请日:2007-02-05

    IPC分类号: H01L21/8242

    摘要: Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.

    摘要翻译: 具有沟槽电容器的存储单元,沟槽电容器至少部分地填充有不能承受在制造存储器芯片期间使用的高温处理而不损害其电参数的材料。 本发明的重要内容是在高温处理之后将沟槽电容器的材料引入沟槽。 根据本发明的方法使得可以使用具有大介电常数的电介质层和由金属材料制成的电极层。 与已知的沟槽电容器相比,沟槽电容器的电性能得到改善。

    Memory cell having a thin insulation collar and memory module
    8.
    发明授权
    Memory cell having a thin insulation collar and memory module 失效
    存储单元具有薄的绝缘环和存储器模块

    公开(公告)号:US07012289B2

    公开(公告)日:2006-03-14

    申请号:US10348148

    申请日:2003-01-21

    CPC分类号: H01L27/10867 H01L27/10832

    摘要: A memory cell has a trench capacitor, in which the area required over a terminal area of the trench capacitor is advantageously reduced by the formation of a particularly thin insulation collar. The insulation collar is reduced to such an extent that although a lateral current is prevented, the formation of a parasitic field-effect transistor is permitted. In order that, however, overall no current flows via the parasitic field-effect transistor, a second parasitic field-effect transistor is disposed in a manner connected in series, but is not turned on. This is achieved by the formation of a thicker second insulation collar that isolates the filling of the trench capacitor from the surrounding substrate.

    摘要翻译: 存储单元具有沟槽电容器,其中通过形成特别薄的绝缘套圈有利地减小了沟槽电容器的端子区域所需的面积。 绝缘套环被减小至尽可能防止横向电流的程度,允许形成寄生场效应晶体管。 然而,为了使整个无电流通过寄生场效应晶体管流过,第二寄生场效应晶体管以串联连接的方式设置,但不导通。 这是通过形成较厚的第二绝缘套圈来实现的,其将沟槽电容器的填充与周围衬底隔离。