公开(公告)号：US06821863B2

公开(公告)日：2004-11-23

申请号：US10348150

申请日：2003-01-21

申请人： Martin Popp ,  Dietmar Temmler ,  Kristin Schupke ,  Uwe Schilling ,  Kerstin Pomplun

发明人： Martin Popp ,  Dietmar Temmler ,  Kristin Schupke ,  Uwe Schilling ,  Kerstin Pomplun

IPC分类号： H01L2176

CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L27/1087

摘要： A semiconductor component has a cavity formed in a monocrystalline silicon substrate. The wall of the cavity is covered by a cover layer, at least in an upper collar region, and a covering layer is then applied to the surface of the silicon substrate using a selective epitaxial growth method. The cavity is thereby covered in the process. The method is physically simple and can be carried out cost-effectively. In particular, the described method can be used in order to cover a trench prior to high-temperature processes during the production of a DRAM memory, and to open the trench once again after the high-temperature processes, in order to provide a trench capacitor.

摘要翻译： 半导体元件具有形成在单晶硅衬底中的空腔。 至少在上衣领区中，空腔的壁被覆盖层覆盖，然后使用选择性外延生长法将覆盖层施加到硅衬底的表面。 因此在该过程中覆盖空腔。 该方法物理上简单，可以经济有效地进行。 特别地，可以使用所描述的方法来在DRAM存储器的制造期间在高温处理之前覆盖沟槽，并且在高温处理之后再次打开沟槽，以便提供沟槽电容器 。

公开(公告)号：US06740595B2

公开(公告)日：2004-05-25

申请号：US10122996

申请日：2002-04-12

申请人： Stephan Kudelka ,  Helmut Tews ,  Alexander Michaelis ,  Uwe Schroeder ,  Martin Popp ,  Kristin Schupke ,  Daniel Koehler

发明人： Stephan Kudelka ,  Helmut Tews ,  Alexander Michaelis ,  Uwe Schroeder ,  Martin Popp ,  Kristin Schupke ,  Daniel Koehler

IPC分类号： H01L21311

CPC分类号： H01L27/1087 ,  H01L21/30604 ,  H01L27/10829 ,  H01L29/66181

摘要： A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.

摘要翻译： 一种通过将NH 4 OH溶液施加到多晶硅中来捕获半导体器件的多晶硅区域中的凹陷的方法。

公开(公告)号：US20080230839A1

公开(公告)日：2008-09-25

申请号：US11728196

申请日：2007-03-23

申请人： Joern Regul ,  Joerg Radecker ,  Olaf Storbeck ,  Kristin Schupke ,  Tobias Mono

发明人： Joern Regul ,  Joerg Radecker ,  Olaf Storbeck ,  Kristin Schupke ,  Tobias Mono

IPC分类号： H01L29/76 ,  H01L21/44 ,  H01L29/94

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L29/6656

摘要： The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process gas which comprises oxygen radicals.

摘要翻译： 本发明涉及一种制造半导体结构的方法，包括以下步骤：制造栅极叠层结构并氧化至少一部分栅叠层结构的侧壁，其中氧化步骤在低于500℃的温度下进行 使用包含氧自由基的工艺气体。

公开(公告)号：US20080003740A1

公开(公告)日：2008-01-03

申请号：US11477581

申请日：2006-06-29

申请人： Odo Wunnicke ,  Peter Moll ,  Kristin Schupke

发明人： Odo Wunnicke ,  Peter Moll ,  Kristin Schupke

IPC分类号： H01L21/8244

CPC分类号： H01L28/91 ,  H01L27/10808 ,  H01L27/10852

摘要： A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads;depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.

摘要翻译： 一种用于形成电容器结构的方法，根据该方法执行以下连续步骤：提供在其表面上具有接触焊盘的基板和设置有至少一个沟槽的介电模，留下暴露的接触焊盘; 在所述沟槽的顶部区域中在所述沟槽的侧壁上形成第一导电层，所述导电层不与所述接触焊盘接触; 沉积第一介电层; 在所述接触焊盘和所述沟槽的侧壁上沉积第二导电层; 沉积第二电介质层; 沉积第三导电层; 以及形成互连所述第一导电层和所述第三导电层的垂直插头。

公开(公告)号：US07005723B2

公开(公告)日：2006-02-28

申请号：US10764264

申请日：2004-01-23

申请人： Armin Tilke ,  Kristin Schupke

发明人： Armin Tilke ,  Kristin Schupke

IPC分类号： H01L27/082

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/41708 ,  H01L29/7378

摘要： In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-terminal layer. A first spacing layer is formed on the wall area of the emitter contact window, and a recess is etched into the substrate within a window specified by the first spacing layer. A base layer contacted by outdiffusion from the base-terminal layer is formed in the recess of the emitter window, and a second spacing layer is formed on the first spacing layer and on the base layer. The second spacing layer is structured for the purpose of specifying a planar terminal pad on the base layer, and an emitter layer is formed on the planar terminal pad.

摘要翻译： 在制造双极晶体管的方法中，提供具有基板表面的半导体基板。 在基板表面上形成用于提供基极端子的基极端子层，并且在基极端子层中形成具有壁区域的发射极窗口。 第一间隔层形成在发射体接触窗口的壁区域上，并且在由第一间隔层指定的窗口内将凹槽蚀刻到衬底中。 在发射器窗口的凹部中形成从基极端子层向外扩散接触的基底层，并且在第一间隔层和基底层上形成第二间隔层。 第二间隔层被构造用于在基底层上指定平面端子焊盘，并且在平面端子焊盘上形成发射极层。

公开(公告)号：US20050275046A1

公开(公告)日：2005-12-15

申请号：US10865763

申请日：2004-06-14

申请人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

发明人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L31/062

CPC分类号： H01L21/28044

摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.

摘要翻译： 通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中， 过渡金属是钛，钽或钴。 对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。 界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。 封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。 在将多晶硅层图案化之前打开氮化物衬垫。 作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。 提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

公开(公告)号：US08835298B2

公开(公告)日：2014-09-16

申请号：US13415492

申请日：2012-03-08

申请人： Sivakumar Kumarasamy ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

发明人： Sivakumar Kumarasamy ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L22/12 ,  H01L22/20

摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni′/Pt layer at a temperature of 130° C.

摘要翻译： 如果检测到Pt残留物，则通过执行包括在SWC工具中在130℃的温度下施加SPM的返工来减少形成含Pt的NiSi后剩余的Pt残余物的量。 实施例包括在半导体衬底上沉积一层Ni / Pt，退火沉积的Ni / Pt层，从退火的Ni / Pt层去除未反应的Ni，退火Ni去除的Ni / Pt层，从退火的Ni中除去未反应的Pt Ni / Pt层，分析未去除Pt残留物的Pt去除Ni / Pt层，如果检测到未反应的Pt残留物，则在SWC工具中将Pt施加到去除的Pt / Ni层上。 可以在130℃的温度下将SPM施加到Pt去除的Ni'/ Pt层上

公开(公告)号：US20130234335A1

公开(公告)日：2013-09-12

申请号：US13414946

申请日：2012-03-08

申请人： Clemens Fitz ,  Jochen Poth ,  Kristin Schupke

发明人： Clemens Fitz ,  Jochen Poth ,  Kristin Schupke

IPC分类号： H01L23/532 ,  H01L21/283

CPC分类号： H01L21/02068 ,  H01L21/28518 ,  H01L21/76829 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.

摘要翻译： 通过在SWC工具中应用HNO3代替SPM清洗工艺，可以消除Ni和Pt残留物。 实施例包括在半导体衬底上沉积一层Ni / Pt，对沉积的Ni / Pt层进行退火，通过在SWC工具中对退火的Ni / Pt层施加HNO 3，从退火的Ni / Pt层去除未反应的Ni，退火Ni 去除Ni / Pt层，并从退火的Ni去除的Ni / Pt层去除未反应的Pt。 实施例包括在基板上形成第一和第二栅极电极，在每个栅电极的相对侧上形成间隔物，并在邻近每个间隔物的衬底上形成含Pt的NiSi，蚀刻间隔物，在第一栅电极上形成拉伸应变层， 在SWC工具中的第一HNO 3，在第二栅电极上形成压应变层，并在SWC工具中施加第二HNO 3。

公开(公告)号：US20080009139A1

公开(公告)日：2008-01-10

申请号：US11481419

申请日：2006-07-05

申请人： Thomas Hecht ,  Kristin Schupke ,  Kevin Bauer ,  Steffen Mueller ,  Henry Bernhardt

发明人： Thomas Hecht ,  Kristin Schupke ,  Kevin Bauer ,  Steffen Mueller ,  Henry Bernhardt

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31111 ,  B81B2203/033 ,  B81C1/00595 ,  B81C2201/0133 ,  B81C2201/0142 ,  H01L27/1087

摘要： A structure in a substrate for the manufacturing of a semiconductor device, wherein a first material and at least one second material are to be etched by at least one etching medium, wherein the at least one second material has a higher etch rate for the at least one etching medium relative to the first material. The at least one second material occupies a space which is at least at one side adjacent to the first material so that an additional etching access to the first material is prepared when at least one etching medium etches the first and the second material.

摘要翻译： 用于制造半导体器件的衬底中的结构，其中第一材料和至少一个第二材料将被至少一个蚀刻介质蚀刻，其中所述至少一个第二材料对于至少一个蚀刻速率具有更高的蚀刻速率 一个蚀刻介质相对于第一材料。 至少一个第二材料占据至少在与第一材料相邻的一侧的空间，使得当至少一个蚀刻介质蚀刻第一和第二材料时，准备对第一材料的另外的蚀刻访问。

公开(公告)号：US20070012662A1

公开(公告)日：2007-01-18

申请号：US11184060

申请日：2005-07-18

申请人： Audrey Dupont ,  Kristin Schupke ,  Stefan Jakschik ,  Alejandro Avellan

发明人： Audrey Dupont ,  Kristin Schupke ,  Stefan Jakschik ,  Alejandro Avellan

IPC分类号： C09K13/00 ,  C09K13/08 ,  B44C1/22 ,  H01L21/461

CPC分类号： H01L21/31111 ,  C09K13/08

摘要： It is one object to devise a solution which is suitable for a wet treatment of Hafnium containing high-k materials. Furthermore, it is an object to devise a use of this solution in the field of semiconductor device manufacturing. It is also an objective of the invention to devise a process to this aim.

摘要翻译： 一个目的是设计一种适用于湿法处理含有高k材料的铪的溶液。 此外，本发明的目的是在半导体器件制造领域中设计出该解决方案。 本发明的目的还在于为此目的设计一个过程。