公开(公告)号：US20060008042A1

公开(公告)日：2006-01-12

申请号：US11225600

申请日：2005-09-13

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Paul Owczarski ,  Martin Schmatz ,  Joseph Stevens

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Paul Owczarski ,  Martin Schmatz ,  Joseph Stevens

IPC分类号： H03D3/24

CPC分类号： H03L7/0995 ,  H04L7/0004 ,  H04L7/0337

摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

摘要翻译： 本发明涉及包括逻辑发射机部分和逻辑接收机部分的统一数字架构。 提供了一种用于在包括发射机和接收机部分的有线媒体上传输数字数据的统一的串行链路系统和方法，发射机部分和接收机部分之一包括锁相环（PLL）电路。 PLL电路包括压控振荡器，分频器，相频检测器，电荷泵和多极环路滤波器。 一个实施例包括具有数字粗略回路和模拟精细回路的双回路PLL。

公开(公告)号：US07447278B2

公开(公告)日：2008-11-04

申请号：US10849693

申请日：2004-05-20

申请人： Christian Menolfi ,  Martin Schmatz ,  Thomas Toifl

发明人： Christian Menolfi ,  Martin Schmatz ,  Thomas Toifl

IPC分类号： H03D1/00

CPC分类号： H04L25/03343 ,  H04L7/0334 ,  H04L25/0272 ,  H04L25/068 ,  H04L25/49 ,  H04L25/497 ,  H04L2025/03477 ,  H04L2025/03802 ,  H04L2025/03808

摘要： The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)−V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).

摘要翻译： 根据本发明的用于发送和接收数据的装置包括用于串行数据传输的发射机（1）和用于接收发射数据信号（g（t））的接收机（3）。 接收器（3）又包括用于利用第一时钟（f 2）对接收到的数据信号（g（t））进行采样并用于产生第一采样值（a）的第一采样锁存器（11）。 接收器（3）还包括用于利用第二时钟（f 1）对第一移位的接收数据信号（g（t）+ V 1）进行采样并用于产生第二采样值（yn）的第二采样锁存器（13）。 接收器（3）还包括用于利用第二时钟（f 1）对第二移位的接收数据信号（g（t）-V 1）进行采样并用于产生第三采样值（zn）的第三采样锁存器（14）。 最后，接收器（3）包括用于从所述第一，第二和第三采样值（an，yn，zn）中恢复数据（dn）的逻辑单元（15）。

公开(公告)号：US20070242741A1

公开(公告)日：2007-10-18

申请号：US11405997

申请日：2006-04-18

申请人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz

发明人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03H7/30

CPC分类号： H04L25/03063

摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

公开(公告)号：US20070101086A1

公开(公告)日：2007-05-03

申请号：US11263344

申请日：2005-10-31

申请人： Frank Ferraiolo ,  Kevin Gower ,  Martin Schmatz

发明人： Frank Ferraiolo ,  Kevin Gower ,  Martin Schmatz

IPC分类号： G06F13/00

CPC分类号： G06F13/4234 ,  G06F13/1689

摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.

摘要翻译： 一种用于在存储器系统中导出时钟的系统，方法和存储介质。 该方法包括在集线器装置处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

公开(公告)号：US20070075785A1

公开(公告)日：2007-04-05

申请号：US11469423

申请日：2006-08-31

申请人： Marcel Kossel ,  Thomas Morf ,  Martin Schmatz ,  Silvan Wehrli

发明人： Marcel Kossel ,  Thomas Morf ,  Martin Schmatz ,  Silvan Wehrli

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/089 ,  H03L7/18

摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.

摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。

公开(公告)号：US20060029177A1

公开(公告)日：2006-02-09

申请号：US11249851

申请日：2005-10-13

申请人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03D3/24

CPC分类号： H03L7/08 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/10 ,  H04L7/0337 ,  H04L2027/0067

摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

公开(公告)号：US20050002475A1

公开(公告)日：2005-01-06

申请号：US10849693

申请日：2004-05-20

申请人： Christian Menolfi ,  Martin Schmatz ,  Thomas Toifl

发明人： Christian Menolfi ,  Martin Schmatz ,  Thomas Toifl

IPC分类号： H04L7/033 ,  H04L25/02 ,  H04L25/03 ,  H04L25/06 ,  H04L25/49 ,  H04L25/497 ,  H03D1/00

CPC分类号： H04L25/03343 ,  H04L7/0334 ,  H04L25/0272 ,  H04L25/068 ,  H04L25/49 ,  H04L25/497 ,  H04L2025/03477 ,  H04L2025/03802 ,  H04L2025/03808

摘要： The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)−V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).

摘要翻译： 根据本发明的用于发送和接收数据的装置包括用于串行数据传输的发射机（1）和用于接收发射数据信号（g（t））的接收机（3）。 接收器（3）又包括用于利用第一时钟（f2）对接收到的数据信号（g（t））进行采样并用于产生第一采样值（a）的第一采样锁存器（11）。 接收器（3）还包括用于利用第二时钟（f1）对第一移位的接收数据信号（g（t）+ V1）进行采样并用于生成第二采样值（yn）的第二采样锁存器（13）。 接收机（3）还包括第三采样锁存器（14），用于对第二时钟（f1）采样第二移位接收数据信号（g（t）-V1）并产生第三采样值（zn）。 最后，接收器（3）包括用于从所述第一，第二和第三采样值（an，yn，zn）中恢复数据（dn）的逻辑单元（15）。

公开(公告)号：US08054867B2

公开(公告)日：2011-11-08

申请号：US12030478

申请日：2008-02-13

申请人： Hayden C. Cranford, Jr. ,  Martin Schmatz

发明人： Hayden C. Cranford, Jr. ,  Martin Schmatz

IPC分类号： H04B1/00

CPC分类号： H04B1/707 ,  H04L5/20 ,  H04L25/45

摘要： An apparatus is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for modulating the additional information signals.

摘要翻译： 提供了一种装置，用于使用用于调制附加信息信号的扩展频谱技术，在同一有线介质上，在有线通信系统内同时发送具有部分重叠频带的数据信号和附加信息信号。

公开(公告)号：US07418069B2

公开(公告)日：2008-08-26

申请号：US11966438

申请日：2007-12-28

申请人： Martin Schmatz ,  Hayden C. Cranford ,  Vernon R. Norman

发明人： Martin Schmatz ,  Hayden C. Cranford ,  Vernon R. Norman

IPC分类号： H04L7/00

CPC分类号： H03L7/091 ,  H03L7/0814 ,  H03L7/089 ,  H04L7/0331

摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

摘要翻译： 本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。 时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。 它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。 设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。 相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

公开(公告)号：US07149269B2

公开(公告)日：2006-12-12

申请号：US10375286

申请日：2003-02-27

申请人： Hayden C. Cranford, Jr. ,  Vernon R. Norman ,  Martin Schmatz

发明人： Hayden C. Cranford, Jr. ,  Vernon R. Norman ,  Martin Schmatz

IPC分类号： H03D3/24

CPC分类号： H03L7/07 ,  H03L7/091 ,  H03L7/0998 ,  H04L7/0025 ,  H04L7/0337

摘要： A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a . . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a . . . φna), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u . . . φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (φ1a . . . φna) depending on the sampling phases (φ1u . . . φnu) and said adjusting signal (AS).

摘要翻译： 用于时钟和数据恢复的接收机包括n个采样锁存器（SL1 ... SLn），用于确定n个采样相位（参见图1a）上的参考信号（Ref 2）的n个采样值（SV1 ... SVn）。 （phina）具有采样锁存输入和采样锁存输出，接收器还包括连接到采样锁存器输出的相位位置分析器（5），用于产生调整信号（AS），用于调整采样相位（phi 1 a。 如果采样值（SV1 ... SVn）偏离设定点，则产生采样相位（phi 1 u。。phinu）的相位插值器（9），连接的采样相位调整单元（6） 其相位位置分析器（5）和相位插值器（9）的输入及其对采样锁存器（SL1 ... SLn）的输出被提供用于产生经调整的采样相位（phi1，...） 取决于采样相位（phi 1 u。。phinu）和所述调整信号（AS）。