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公开(公告)号：US20110195530A1
公开(公告)日：2011-08-11
申请号：US12982032
申请日：2010-12-30
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
摘要翻译： 一种包括形成中间产品的方法，所述中间产品被配置为包括布线基板，所述布线基板包括多个第一电极，多个第二电极和多个测试电极，第一半导体芯片安装在所述布线基板上并且包括多个 分别与第一电极电连接的第一焊盘和堆叠在第一半导体芯片上并包括分别电连接到第二电极的多个第二焊盘的第二半导体芯片; 封装第一和第二半导体芯片; 以及在封装了第一和第二半导体芯片之后，通过使用测试电极对第一和第二半导体芯片进行电测试。
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公开(公告)号：US07633146B2
公开(公告)日：2009-12-15
申请号：US12033170
申请日：2008-02-19
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Detachably mountable memory card featuring a memory chip(s) and a control chip includes a substrate of an insulating material, conductive layers provided on a first main surface of the substrate, a plurality of external electrode terminals exposed to the opposing, second main surface of the substrate, and conductive portions electrically connecting the conductive layers with corresponding ones of the external electrode terminals. The memory chip(s) and the control chip are electrically connected with ones of the conductive layers. The memory card also includes an encapsulating insulating layer covering the first main surface of the substrate, the fixedly disposed memory and control chips thereon, and the conductive layers, the encapsulating insulating layer having an exposed flat surface representing one main plane surface of the finished memory card, and the second main surface of the substrate representing another main plane surface of the memory card with the exposed external electrode terminals.
摘要翻译： 具有存储芯片和控制芯片的可拆卸安装的存储卡包括绝缘材料的基板，设置在基板的第一主表面上的导电层，暴露于相对的第二主表面的多个外部电极端子 所述基板和将所述导电层与对应的所述外部电极端子电连接的导电部分。 存储芯片和控制芯片与导电层中的一个电连接。 存储卡还包括覆盖基板的第一主表面的封装绝缘层，其上的固定设置的存储器和控制芯片，以及导电层，封装绝缘层具有表示成品存储器的一个主平面的暴露的平坦表面 卡，并且表示存储卡的另一个主平面的露出的外部电极端子的基板的第二主表面。
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公开(公告)号：US06686663B2
公开(公告)日：2004-02-03
申请号：US10194224
申请日：2002-07-15
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L2348
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Two memory chips mounted over a base substrate have the same external size and a flash memory of the same memory capacity formed thereon. These memory chips are mounted over the base substrate with one of them being overlapped with the upper portion of the other one, and they are stacked with their faces being turned in the same direction. The bonding pads BP of one of the memory chips are disposed in the vicinity of the bonding pads BP of the other memory chip. In addition, the upper memory chip is stacked over the lower memory chip in such a way that the upper memory chip is slid in a direction (X direction) parallel to the one side of the lower memory chip and in a direction (Y direction) perpendicular thereto in order to prevent partial overlapping of it with the bonding pads BP of the lower memory chip.
摘要翻译： 安装在基底基板上的两个存储芯片具有相同的外部尺寸和形成在其上的相同存储器容量的闪存。 这些存储器芯片安装在基底上，其中一个与另一个的上部重叠，并且它们被堆叠成使它们的面沿同一方向转动。 一个存储芯片的接合焊盘BP设置在另一个存储芯片的接合焊盘BP附近。 此外，上部存储器芯片堆叠在下部存储器芯片上，使得上部存储器芯片沿着与下部存储器芯片的一侧平行的方向（X方向）和沿（Y方向）的方向滑动， 与其垂直，以防止其与下部存储器芯片的接合焊盘BP的部分重叠。
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公开(公告)号：US08067251B2
公开(公告)日：2011-11-29
申请号：US12982032
申请日：2010-12-30
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
摘要翻译： 一种包括形成中间产品的方法，所述中间产品被配置为包括布线基板，所述布线基板包括多个第一电极，多个第二电极和多个测试电极，第一半导体芯片安装在所述布线基板上并且包括多个 分别与第一电极电连接的第一焊盘和堆叠在第一半导体芯片上并包括分别电连接到第二电极的多个第二焊盘的第二半导体芯片; 封装第一和第二半导体芯片; 以及在封装了第一和第二半导体芯片之后，通过使用测试电极对第一和第二半导体芯片进行电测试。
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公开(公告)号：US20060170084A1
公开(公告)日：2006-08-03
申请号：US11392689
申请日：2006-03-30
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L23/495
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A memory card containing a resin sealed stacking of plural semiconductor chips which are rear surface mounted over a main surface of a base substrate, the rear surface of the substrate being provided with external connection terminals. The relatively lower ones of the stacked semiconductor chips include a memory circuit and may be larger in size than the uppermost chip which contains a control circuit. Resin sealed wiring connections between bonding pads on the main surface of the respective chips and corresponding ones of electrodes on the main surface of the substrate are arranged so as to avoid crossovers between them, with respect to a plan view thereof. A resin cap may be used to cover the main surface side of the base substrate, which has the resin sealed semiconductor chips mounted thereon.
摘要翻译： 一种存储卡，其包含后表面安装在基底基板的主表面上的多个半导体芯片的树脂密封堆叠，所述基板的后表面设置有外部连接端子。 层叠的半导体芯片中相对较低的半导体芯片包括存储器电路，并且其尺寸可以大于包含控制电路的最上面的芯片。 布置相应芯片主表面上的焊盘与基板主表面上的相应电极之间的树脂密封接线，以避免它们之间的交叉。 可以使用树脂盖来覆盖安装在其上的树脂密封半导体芯片的基底基板的主表面侧。
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公开(公告)号：US20120013027A1
公开(公告)日：2012-01-19
申请号：US13243583
申请日：2011-09-23
申请人： Masachika MASUDA , Toshihiko Usami
发明人： Masachika MASUDA , Toshihiko Usami
IPC分类号： H01L25/03
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
摘要翻译： 一种包括形成中间产品的方法，所述中间产品被配置为包括布线基板，所述布线基板包括多个第一电极，多个第二电极和多个测试电极，第一半导体芯片安装在所述布线基板上并且包括多个 分别与第一电极电连接的第一焊盘和堆叠在第一半导体芯片上并包括分别电连接到第二电极的多个第二焊盘的第二半导体芯片; 封装第一和第二半导体芯片; 以及在封装了第一和第二半导体芯片之后，通过使用测试电极对第一和第二半导体芯片进行电测试。
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公开(公告)号：US20080290488A1
公开(公告)日：2008-11-27
申请号：US12033170
申请日：2008-02-19
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Detachably mountable memory card featuring a memory chip(s) and a control chip includes a substrate of an insulating material, conductive layers provided on a first main surface of the substrate, a plurality of external electrode terminals exposed to the opposing, second main surface of the substrate, and conductive portions electrically connecting the conductive layers with corresponding ones of the external electrode terminals. The memory chip(s) and the control chip are electrically connected with ones of the conductive layers. The memory card also includes an encapsulating insulating layer covering the first main surface of the substrate, the fixedly disposed memory and control chips thereon, and the conductive layers, the encapsulating insulating layer having an exposed flat surface representing one main plane surface of the finished memory card, and the second main surface of the substrate representing another main plane surface of the memory card with the exposed external electrode terminals.
摘要翻译： 具有存储芯片和控制芯片的可拆卸安装的存储卡包括绝缘材料的基板，设置在基板的第一主表面上的导电层，暴露于相对的第二主表面的多个外部电极端子 所述基板和将所述导电层与对应的所述外部电极端子电连接的导电部分。 存储芯片和控制芯片与导电层中的一个电连接。 存储卡还包括覆盖基板的第一主表面的封装绝缘层，其上的固定设置的存储器和控制芯片，以及导电层，封装绝缘层具有表示成品存储器的一个主平面的暴露的平坦表面 卡，并且表示存储卡的另一个主平面的露出的外部电极端子的基板的第二主表面。
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公开(公告)号：US07348668B2
公开(公告)日：2008-03-25
申请号：US11392689
申请日：2006-03-30
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A memory card containing a resin sealed stacking of plural semiconductor chips which are rear surface mounted over a main surface of a base substrate, the rear surface of the substrate being provided with external connection terminals. The relatively lower ones of the stacked semiconductor chips include a memory circuit and may be larger in size than the uppermost chip which contains a control circuit. Resin sealed wiring connections between bonding pads on the main surface of the respective chips and corresponding ones of electrodes on the main surface of the substrate are arranged so as to avoid crossovers between them, with respect to a plan view thereof. A resin cap may be used to cover the main surface side of the base substrate, which has the resin sealed semiconductor chips mounted thereon.
摘要翻译： 一种存储卡，其包含后表面安装在基底基板的主表面上的多个半导体芯片的树脂密封堆叠，所述基板的后表面设置有外部连接端子。 层叠的半导体芯片中相对较低的半导体芯片包括存储器电路，并且其尺寸可以大于包含控制电路的最上面的芯片。 布置相应芯片主表面上的焊盘与基板主表面上的相应电极之间的树脂密封接线，以避免它们之间的交叉。 可以使用树脂盖来覆盖安装在其上的树脂密封半导体芯片的基底基板的主表面侧。
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公开(公告)号：US08502395B2
公开(公告)日：2013-08-06
申请号：US13413914
申请日：2012-03-07
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires.
摘要翻译： 一种半导体器件，其特征在于具有由第一边缘和相对的第二边缘限定的第一表面的基板，形成在第一表面上的电极焊盘，安装在第一边缘和电极焊盘之间的第一表面上的第一半导体芯片， 每个电连接到对应的电极焊盘，堆叠在第一半导体芯片上的第二半导体芯片，并且包括每个电连接到相应的电极焊盘的第二焊盘;第三半导体芯片，安装在第二边缘和第二半导体衬底之间的衬底的第一表面上 电极焊盘，并且包括每个电连接到相应的电极焊盘的第三焊盘，其中一个电极焊盘电连接到一个第一焊盘，一个第二焊盘和一个第三焊盘，另一个电极焊盘电连接到第一焊盘和第二焊盘 通过单独的接合线。
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公开(公告)号：US08159062B2
公开(公告)日：2012-04-17
申请号：US13243583
申请日：2011-09-23
申请人： Masachika Masuda , Toshihiko Usami
发明人： Masachika Masuda , Toshihiko Usami
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , B82Y10/00 , G06K19/077 , G06K19/07732 , G11C5/02 , H01L22/32 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L23/5388 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/074 , H01L2224/04042 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H05K1/0268 , H05K1/117 , H05K3/284 , H05K2201/10159 , H05K2203/1572 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
摘要翻译： 一种包括形成中间产品的方法，所述中间产品被配置为包括布线基板，所述布线基板包括多个第一电极，多个第二电极和多个测试电极，第一半导体芯片安装在所述布线基板上并且包括多个 分别与第一电极电连接的第一焊盘和堆叠在第一半导体芯片上并包括分别电连接到第二电极的多个第二焊盘的第二半导体芯片; 封装第一和第二半导体芯片; 以及在封装了第一和第二半导体芯片之后，通过使用测试电极对第一和第二半导体芯片进行电测试。
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