公开(公告)号：US06487133B2

公开(公告)日：2002-11-26

申请号：US09898033

申请日：2001-07-05

申请人： Masaharu Wada ,  Kenji Tsuchida ,  Atsushi Takeuchi

发明人： Masaharu Wada ,  Kenji Tsuchida ,  Atsushi Takeuchi

IPC分类号： G11C700

CPC分类号： G11C7/06

摘要： The present invention relates to overdrive circuits for generating an operational potential of a sense amplifier. For example, a switch circuit is used to connect a drive node of the sense amplifier with a overdrive potential generation circuit for generating an overdrive potential to be applied to bit lines. A restoration potential generation circuit comprises a push-pull regulator circuit for generating a restoration potential to be applied to bit lines. Consequently, the restoration potential generation circuit can directly connect with the sense amplifier's drive node.

公开(公告)号：US06452860B2

公开(公告)日：2002-09-17

申请号：US09871646

申请日：2001-06-04

申请人： Masaharu Wada ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Atsushi Takeuchi ,  Toshimi Ikeda ,  Kuninori Kawabata

发明人： Masaharu Wada ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Atsushi Takeuchi ,  Toshimi Ikeda ,  Kuninori Kawabata

IPC分类号： G11C800

CPC分类号： G11C5/063

摘要： A semiconductor memory device has a segment type word line structure and comprises a plurality of main word lines and a plurality of sub word lines which are arranged at different levels. The semiconductor memory device is provided with a memory cell array divided into a plurality of cell array blocks. A plurality of sub row decoder areas, each for selecting one of the sub word lines, are defined between the cell array blocks. A plurality of first metal wiring lines formed by use of the same wiring layer as the main word lines are provided. The first metal wiring lines pass across the sub row decoder areas and the cell array blocks.

摘要翻译： 半导体存储器件具有段类型的字线结构，并且包括多个主字线和排列在不同电平的多个子字线。 半导体存储器件设置有分成多个单元阵列块的存储单元阵列。 在单元阵列块之间定义多个用于选择一个子字线的子行解码器区域。 提供了通过使用与主字线相同的布线层形成的多个第一金属布线。 第一金属布线穿过子行解码器区域和单元阵列块。

公开(公告)号：US06608514B1

公开(公告)日：2003-08-19

申请号：US09511352

申请日：2000-02-23

申请人： Hironobu Akita ,  Katsuaki Isobe ,  Masaharu Wada ,  Kenji Tsuchida ,  Haruki Toda

发明人： Hironobu Akita ,  Katsuaki Isobe ,  Masaharu Wada ,  Kenji Tsuchida ,  Haruki Toda

IPC分类号： H03K300

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/00006 ,  H03K5/135

摘要： A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock signal aTx outputted from the OR circuit, has twice the frequency of the external clock signal CK, and is advanced in phase by the signal delay time in the off-chip driver.

摘要翻译： 时钟信号发生器电路包括片外驱动器，用于输出与外部时钟信号CK同步的第一内部时钟信号Tu的第一时钟控制电路，用于将第二内部时钟信号Td 180°输出的第二时钟控制电路， 与外部时钟信号CK的同相;第三时钟控制电路，用于输出与第一时钟信号Tu同步的第三内部时钟信号aTx1并至少在芯片外驱动器中的信号延迟时间相位前进;第四时钟控制电路， 时钟控制电路，用于输出与第二时钟信号Td同步的第四内部时钟信号aTx2并至少在片外驱动器中的信号延迟时间相位前进;第三和第四内部时钟信号aTx1， 输入aTx2并输出第五内部时钟信号aTx，以及第五时钟控制电路，用于输出与f同步的第六内部时钟信号Tx 从OR电路输出的第四内部时钟信号aTx具有外部时钟信号CK的两倍频率，并且在片外驱动器中相位提前信号延迟时间。

公开(公告)号：US06326834B1

公开(公告)日：2001-12-04

申请号：US09602896

申请日：2000-06-23

申请人： Hironobu Akita ,  Masaharu Wada ,  Kenji Tsuchida ,  Hironori Banba

发明人： Hironobu Akita ,  Masaharu Wada ,  Kenji Tsuchida ,  Hironori Banba

IPC分类号： G05F110

CPC分类号： H02M3/073

摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.

摘要翻译： 用于对多个电容器的各个侧面节点进行充电的第一晶体管分别连接到电容器的这些节点。 用于输出每个电容器的电荷的第二晶体管分别连接在电容器的相应的一个侧面节点和输出端子之间。 用于将电容器的另一侧节点的电荷转移到其他节点的多个第三晶体管连接到相应的其他节点。 每个电容器的电荷通过顺序地控制第三晶体管，通过一个路径从高电位的节点被串行地传递到较低电位的节点，或者每个电容器的电荷在高电位的任意节点之间并行传送 潜在和低节点通过多个路径。 通过这些操作，每个电容器的电荷被再循环。

公开(公告)号：US06754122B2

公开(公告)日：2004-06-22

申请号：US10358389

申请日：2003-02-05

申请人： Masaharu Wada ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Toshimi Ikeda

发明人： Masaharu Wada ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Toshimi Ikeda

IPC分类号： G11C702

CPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/4091

摘要： After data readout, in equalizing a complementary pair of bit lines one of which has been overdriven with an overdrive voltage, excessive charges on the overdriven bit line are discharged by a discharge circuit. By adjusting the discharge period of the discharge circuit, the potential to which the bit lines are equalized is adjusted.

摘要翻译： 在数据读出之后，为了均衡互补的一对位线，其中一个已经用过驱动电压过驱动，过驱动位线上的过量电荷被放电电路放电。 通过调节放电电路的放电周期，调整位线均衡的电位。

公开(公告)号：US06433619B1

公开(公告)日：2002-08-13

申请号：US09972905

申请日：2001-10-10

申请人： Hironobu Akita ,  Masaharu Wada ,  Kenji Tsuchida ,  Hironori Banba

发明人： Hironobu Akita ,  Masaharu Wada ,  Kenji Tsuchida ,  Hironori Banba

IPC分类号： G05F110

摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.

公开(公告)号：US06483756B2

公开(公告)日：2002-11-19

申请号：US09984270

申请日：2001-10-29

申请人： Atsushi Takeuchi ,  Masaharu Wada

发明人： Atsushi Takeuchi ,  Masaharu Wada

IPC分类号： G11C1604

CPC分类号： G11C5/143 ,  G11C8/08

摘要： A semiconductor device includes a word line that is reset to a negative voltage when the word line is unselected. The semiconductor device further includes a sequence circuit that clamps the word line to a first fixed voltage, until a fixed power-supply voltage that is supplied to a memory cell connected to the word line reaches a second fixed voltage, at a time of starting power supply. Thus, the semiconductor device can prevent a negative power-supply voltage used for resetting the word line from rising, and can reduce consumed energy.

公开(公告)号：US08675431B2

公开(公告)日：2014-03-18

申请号：US13425364

申请日：2012-03-20

申请人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

发明人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

IPC分类号： G11C29/00

CPC分类号： G11C29/702 ,  G11C29/785 ,  G11C2029/0401 ,  G11C2029/4402

摘要： A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

摘要翻译： 第一半导体芯片的存储单元阵列包括正常单元阵列和备用单元阵列。 第一缺陷地址数据输出电路输出指示存储单元阵列中缺陷存储单元地址的第一缺陷地址数据。 第一比较电路将地址数据与第一缺陷地址数据进行比较，并在匹配的情况下输出第一匹配信号。 第二缺陷地址数据输出电路输出指示存储单元阵列中缺陷存储单元的地址的第二缺陷地址数据。 第二比较电路将地址数据与第二缺陷地址数据进行比较，并在匹配的情况下输出第二匹配信号。

公开(公告)号：US20120091803A1

公开(公告)日：2012-04-19

申请号：US13022888

申请日：2011-02-08

申请人： Masaharu Wada

发明人： Masaharu Wada

IPC分类号： G05F1/56

CPC分类号： G05F3/242 ,  G05F3/30 ,  Y10T307/406

摘要： A constant voltage constant current generation circuit includes a first transistor, a first resistor connected between the first terminal and a second potential, a first diode connected in series with the first resistor, and a first operational amplifier which outputs a first control signal to a control terminal of the first transistor. The constant voltage constant current generation circuit includes a current output circuit which outputs a constant current from a current output terminal according to the first control signal, a second transistor through which a second current flows, the second current obtained by mirroring a first current flowing through the first transistor, a second resistor connected between the voltage output terminal and the second potential. The constant voltage constant current generation circuit includes a current source which outputs a current to the voltage output terminal, and which has negative current characteristics with respect to a temperature change, and a reference voltage output circuit which outputs the reference voltage from a reference voltage terminal.

摘要翻译： 恒压恒流产生电路包括：第一晶体管，连接在第一端子和第二电位之间的第一电阻器，与第一电阻器串联连接的第一二极管;以及第一运算放大器，其将第一控制信号输出到控制器 端子的第一晶体管。 恒压恒定电流产生电路包括电流输出电路，该电流输出电路根据第一控制信号输出来自电流输出端的恒定电流，第二电流流过的第二晶体管，通过镜像流过第一电流而获得的第二电流 第一晶体管，连接在电压输出端和第二电位之间的第二电阻。 恒压恒定电流产生电路包括：电流源，其向电压输出端子输出电流，并且相对于温度变化具有负电流特性;以及参考电压输出电路，其从参考电压端子输出参考电压 。

公开(公告)号：US20090261885A1

公开(公告)日：2009-10-22

申请号：US12388755

申请日：2009-02-19

申请人： Masaharu Wada

发明人： Masaharu Wada

IPC分类号： H03L5/00

CPC分类号： H03K3/356139 ,  G06F1/24 ,  H03K17/223

摘要： When a low supply potential has risen while a high supply potential has not risen, a logical value “0” is output as an output signal by applying a ground potential to an input terminal of a latch circuit through a capacitor. On the other hand, when the high supply potential has risen while the low supply potential has not risen, a logical value “0” is output as an output signal by converting the high supply potential into the ground potential by the level shifter. If both the low supply potential and the high supply potential have risen, the logical value “1” is output as an output signal by converting the ground potential into the high supply potential by the level shifter.

摘要翻译： 当低电源电位升高而高电源电位尚未升高时，通过电容器将锁存电路的输入端施加接地电位作为输出信号输出逻辑值“0”。 另一方面，当低供电电位未上升时，当高供电电位上升时，通过电平移位器将高电源电位转换为地电位，输出逻辑值“0”作为输出信号。 如果低电源电位和高电源电位都升高，则通过电平移位器将地电位转换为高电源电位来输出逻辑值“1”作为输出信号。