VARIABLE INTAKE APPARATUS FOR V-TYPE INTERNAL COMBUSTION ENGINE
    4.
    发明申请
    VARIABLE INTAKE APPARATUS FOR V-TYPE INTERNAL COMBUSTION ENGINE 有权
    用于V型内燃机的可变输入装置

    公开(公告)号:US20090250025A1

    公开(公告)日:2009-10-08

    申请号:US12309883

    申请日:2007-08-06

    IPC分类号: F01L1/34 F02M35/10

    摘要: In a variable intake apparatus for a V-type internal combustion engine, each of plural intake pipes is separated from a surge tank by a partition wall, and communication ports, provided in the partition wall for the respective intake pipes, are opened and closed by respective variable intake valves to adjust length of intake passages. The variable intake valves in one of two parallel rows are offset from the variable intake valves in the other row. The variable intake valves are opened and closed by turning the turning shafts to which the variable intake valves are connected. Further, a synchronization mechanism synchronously turns the turning shafts (5a; 5b), and is connected between the paired turning shafts. The turning motion of one turning shaft is transmitted to the other turning shaft via the synchronization mechanism, and the variable intake valves are synchronously opened and closed.

    摘要翻译: 在用于V型内燃机的可变进气装置中,多个进气管中的每一个通过分隔壁与缓冲罐隔开,并且设置在各个进气管的分隔壁中的连通口由 相应的可变进气门,以调节进气通道的长度。 两个平行排中的一个可变进气门偏离另一排中的可变进气门。 可变进气门通过转动连接可变进气门的转动轴而打开和关闭。 此外,同步机构同步地转动转动轴(5a; 5b),并且连接在成对的转动轴之间。 一个转动轴的转动运动通过同步机构传递到另一个转动轴,可变进气门同步打开和关闭。

    Semiconductor memory device
    5.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US20050286331A1

    公开(公告)日:2005-12-29

    申请号:US11154625

    申请日:2005-06-17

    IPC分类号: G11C7/00 G11C11/406

    摘要: Disclosed is a semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

    摘要翻译: 公开了一种包括片上ECC电路并且具有数据保持模式的半导体存储器件,该数据保持模式按状态转换的顺序包括纠错电路的编码状态EEST,其中纠错电路执行奇偶位的计算 的存储器单元的数据,其中存储器单元以比普通自刷新更短的周期的脉冲串自刷新的脉冲串自刷新状态BSST,电源关闭状态PFST,其中内部电源电路 内部电源电路被部分关断的通电状态PNST和通过纠错电路校正存储单元的错误的纠错电路的解码状态EDST被部分关闭。 在编码状态下从数据保持模式退出的命令的情况下,可以转换到空闲状态IST,以便可以从解码状态EDST到BSST进行重新输入。

    Partial broadcast method in parallel computer and a parallel computer
suitable therefor
    6.
    发明授权
    Partial broadcast method in parallel computer and a parallel computer suitable therefor 失效
    并行计算机中的部分广播方法和适用于其的并行计算机

    公开(公告)号:US5826049A

    公开(公告)日:1998-10-20

    申请号:US916630

    申请日:1992-07-22

    CPC分类号: G06F15/17368

    摘要: In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

    摘要翻译: 为了确定消息到接收端处理器组的传送路径,处理器包括路由位生成电路,并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。 为了定义接收端处理器组的范围,网络包括传送控制电路。 交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。 当在输出端口的下游方向上从输入端口传送部分广播消息时,确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口,由此 特定的部分广播消息从相同的输出端口传送。

    Switch circuit comprised of logically split switches for parallel
transfer of messages and a parallel processor system using the same
    7.
    发明授权
    Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same 失效
    由用于并行传送消息的逻辑分割开关组成的开关电路和使用该开关的并行处理器系统

    公开(公告)号:US5754792A

    公开(公告)日:1998-05-19

    申请号:US34359

    申请日:1993-03-19

    摘要: A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch. By means of an input port select circuit provided in association with each of the output ports, an output request for the packet from the input port belonging to the split crossbar switch to which the associated output port belongs is accepted, while output requests for the packets from the input ports belonging to the other split crossbar switches are inhibited from being accepted, whereby transfer of broadcast packets are inhibited between the split crossbar switches belonging to a physically same crossbar switch. Such situation can be evaded in which same broadcast packets arrive at one and the same processor a number of times.

    摘要翻译: 一种并行处理器系统,包括多个处理器。 当从不同的端口输入相同的目的地PE号码的分组时,通过使用各自的加法电路,分别将目的地PE号码分别与不同的输入端口所属的分离的交叉开关的前导端口的ID号相加,从而确定传送 目标输出端口为数据包。 通过划分交叉开关来实现具有不同数量的输入/输出端口的多个分开的交叉开关。 通过与每个输出端口相关联地提供的输入端口选择电路,接收来自属于相关联的输出端口所属的分离交叉开关的输入端口的分组的输出请求,同时对分组的输出请求 从属于其他分割交叉开关的输入端口被禁止被接受,从而在属于物理上相同的交叉开关的分开的交叉开关之间禁止广播分组的传送。 可以避免这种情况,其中相同的广播分组多次到达同一个处理器。

    Apparatus for mixing and baking of bread
    9.
    发明授权
    Apparatus for mixing and baking of bread 失效
    用于混合和烘烤面包的设备

    公开(公告)号:US4294166A

    公开(公告)日:1981-10-13

    申请号:US157189

    申请日:1980-06-06

    申请人: Shigeo Takeuchi

    发明人: Shigeo Takeuchi

    摘要: A breadmaking method and apparatus particularly adapted for household use. A combined trough and baking-pan unit is removably mounted on a lift table arranged in the oven and, when raised, is automatically covered by a downwardly spring-biased closure member and receives a measured amount of water as allowed to fall down through the bottom port of a water tank provided above and through holes formed in the closure member. Also provided are agitator means which are operable to act upon the mixture in the combined trough and baking pan unit raised. For fermentation and degassing of the dough thus formed in the unit, the lift table is lowered to its bottom position and held there for an appropriate length of time and thereafter the oven temperature is raised to a suitable level. The oven heater can also serve to heat the water held in the tank preliminarily to an optimum temperature and thus enables any inexperienced person to make palatable bread at all seasons independently of the external atmospheric temperature with ease.

    摘要翻译: 一种特别适合家庭使用的面包制作方法和装置。 组合的槽和烤盘单元可移除地安装在布置在烤箱中的升降台上,并且当升高时,被向下弹簧偏压的关闭构件自动地覆盖,并且允许测量量的水被允许通过底部 提供在上面的水槽的端口和形成在封闭构件中的通孔。 还提供了搅拌器装置,其可操作以作用于组合槽中的混合物和升高的烤盘单元。 对于在该单元中形成的生面团的发酵和脱气,将升降台降低到其底部位置,并将其保持在适当的时间长度上,然后将炉温提高至合适的水平。 烤箱加热器还可以预先将保存在罐中的水加热到最佳温度,从而使任何无经验的人能够轻松地在独立于外部大气温度的情况下,在所有季节制作可口的面包。