公开(公告)号：US6100579A

公开(公告)日：2000-08-08

申请号：US983010

申请日：1998-07-02

申请人： Masahisa Sonoda ,  Susumu Shuto ,  Miwa Tanaka ,  Toshiaki Idaka ,  Hiroaki Tsunoda ,  Hitoshi Araki

发明人： Masahisa Sonoda ,  Susumu Shuto ,  Miwa Tanaka ,  Toshiaki Idaka ,  Hiroaki Tsunoda ,  Hitoshi Araki

IPC分类号： H01L21/8247 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/00 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L23/58 ,  H01L21/469

CPC分类号： H01L23/291 ,  H01L23/5329 ,  H01L23/564 ,  H01L27/10844 ,  H01L2924/0002

摘要： In manufacturing a CVD film (interlayer insulating film or passivation film) using material gases containing a gas having Si--H combination, the amount of Si--H combination in the CVD film (12, 31, 32, 33, 34, 47, 48, 49, 57, 59) is set to 0.6.times.10.sup.21 cm.sup.-3 or less to thereby suppress the formation of electron traps in the gate oxide film or tunnel oxide film and prevent variations in the threshold of transistors. In addition, the moisture resistance can be improved by setting the refractive index of the CVD film to 1.65 or more or by setting the concentration of nitrogen in the CVD film to 3.times.10.sup.21 cm.sup.-3 or more.

摘要翻译： PCT No.PCT / JP97 / 01378 Sec。 371日期：1998年7月2日 102（e）日期1998年7月2日PCT 1997年4月22日PCT PCT。 公开号WO97 / 40533 日期1997年10月30日在使用含有Si-H组合气体的原料气体制造CVD膜（层间绝缘膜或钝化膜）时，CVD膜中的Si-H组合量（12,31,32,33， 34,47,48,49,57,59）设定为0.6×10 21 cm -3以下，从而抑制栅极氧化膜或隧道氧化物膜中的电子陷阱的形成，并防止晶体管的阈值的变化。 此外，通过将CVD膜的折射率设定为1.65以上或通过将CVD膜中的氮浓度设定为3×10 21 cm -3以上，可以提高耐湿性。

公开(公告)号：US07368342B2

公开(公告)日：2008-05-06

申请号：US10948661

申请日：2004-09-24

申请人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Eiji Sakagami ,  Hidemi Kanetaka ,  Kenji Matsuzaki ,  Takanori Matsumoto

发明人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Eiji Sakagami ,  Hidemi Kanetaka ,  Kenji Matsuzaki ,  Takanori Matsumoto

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/76232 ,  H01L21/823481 ,  H01L21/823878

摘要： A method for manufacturing a semiconductor device includes forming a gate-insulating film on a semiconductor substrate; forming a gate electrode on the gate-insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, the gate insulating film and the semiconductor substrate to form a trench which is used to electrically isolate a device region for forming a device from the remainder region on the substrate top surface; and etching the inside of the trench using a gas containing Cl2 and HBr with a different condition from the etching condition of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成栅极绝缘膜; 在所述栅极绝缘膜上形成与所述半导体衬底电绝缘的栅电极; 蚀刻栅电极，栅极绝缘膜和半导体衬底以形成用于将用于形成器件的器件区域与衬底顶表面上的其余区域电隔离的沟槽; 并使用与半导体衬底的蚀刻条件不同的条件，使用含有Cl 2 2和HBr的气体来蚀刻沟槽的内部。

公开(公告)号：US06984858B2

公开(公告)日：2006-01-10

申请号：US10293254

申请日：2002-11-14

申请人： Masahisa Sonoda ,  Tadashi Iguchi ,  Hiroaki Tsunoda ,  Eiji Sakagami

发明人： Masahisa Sonoda ,  Tadashi Iguchi ,  Hiroaki Tsunoda ,  Eiji Sakagami

IPC分类号： H01L27/108

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823462

摘要： In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.

摘要翻译： 在包括多个元件区域的半导体器件和基于将元件区域彼此电隔离的STI（浅沟槽隔离）的元件隔离区域中，每个元件区域包括： 一个通道区域 形成为在水平方向夹着沟道区的源/漏区; 形成在通道区域上并且鸟嘴的角度为1度或更小的栅极绝缘膜，所述鸟喙从元件隔离区的与面向沟道区域的表面相对的表面形成， 大致垂直于源极/漏极区域夹着沟道区域的方向的水平方向; 以及形成在栅极绝缘膜上的栅极电极层。

公开(公告)号：US06933194B2

公开(公告)日：2005-08-23

申请号：US10670249

申请日：2003-09-26

申请人： Kazuhito Narita ,  Eiji Sakagami ,  Hiroaki Tsunoda ,  Masahisa Sonoda ,  Hideyuki Kobayashi

发明人： Kazuhito Narita ,  Eiji Sakagami ,  Hiroaki Tsunoda ,  Masahisa Sonoda ,  Hideyuki Kobayashi

IPC分类号： H01L21/28 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/115

摘要： A method of manufacturing a semiconductor device including forming a laminate structure which includes a gate insulation film on a semiconductor substrate and a gate electrode material film on the gate insulation film, processing the gate electrode material film to obtain a gate electrode having a reverse tapered cross section, and forming a device isolation insulation film in direct contact with a side surface of the gate electrode.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底上形成包括栅极绝缘膜的层叠结构和栅极绝缘膜上的栅电极材料膜，处理栅电极材料膜以获得具有反向锥形交叉的栅电极 并且形成与栅电极的侧表面直接接触的器件隔离绝缘膜。

公开(公告)号：US06642568B2

公开(公告)日：2003-11-04

申请号：US09892487

申请日：2001-06-28

申请人： Kazuhito Narita ,  Eiji Sakagami ,  Hiroaki Tsunoda ,  Masahisa Sonoda ,  Hideyuki Kobayashi

发明人： Kazuhito Narita ,  Eiji Sakagami ,  Hiroaki Tsunoda ,  Masahisa Sonoda ,  Hideyuki Kobayashi

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/115

摘要： This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.

公开(公告)号：US20080090378A1

公开(公告)日：2008-04-17

申请号：US11868164

申请日：2007-10-05

申请人： Hiroaki Tsunoda ,  Masahisa Sonoda

发明人： Hiroaki Tsunoda ,  Masahisa Sonoda

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of fabricating a semiconductor device includes forming a trench in a semiconductor substrate by a reactive ion etching (RIE) method, the trench having an inner surface, treating the trench with diluted hydrofluoric acid, treating the interior of the trench by a hydrofluoric acid vapor phase cleaning (HFVPC) method, forming a high temperature oxide (HTO) film along the inner surface of the trench, and forming an element isolation insulating film inside the HTO film in the trench so that the trench is filled with the element isolation insulating film.

摘要翻译： 制造半导体器件的方法包括通过反应离子蚀刻（RIE）法在半导体衬底中形成沟槽，沟槽具有内表面，用稀氢氟酸处理沟槽，用氢氟酸处理沟槽的内部 气相清洗（HFVPC）方法，沿着沟槽的内表面形成高温氧化物（HTO）膜，并且在沟槽内的HTO膜内部形成元件隔离绝缘膜，使沟槽填充元件绝缘隔离层 电影。

公开(公告)号：US20050116304A1

公开(公告)日：2005-06-02

申请号：US11031044

申请日：2005-01-10

申请人： Masahisa Sonoda ,  Tadashi Iguchi ,  Hiroaki Tsunoda ,  Eiji Sakagami

发明人： Masahisa Sonoda ,  Tadashi Iguchi ,  Hiroaki Tsunoda ,  Eiji Sakagami

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823462

摘要： In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.

摘要翻译： 在包括多个元件区域的半导体器件和基于将元件区域彼此电隔离的STI（浅沟槽隔离）的元件隔离区域中，每个元件区域包括： 一个通道区域 形成为在水平方向夹着沟道区的源/漏区; 形成在通道区域上并且鸟嘴的角度为1度或更小的栅极绝缘膜，所述鸟喙从元件隔离区的与面向沟道区域的表面相对的表面形成， 大致垂直于源极/漏极区域夹着沟道区域的方向的水平方向; 以及形成在栅极绝缘膜上的栅极电极层。

公开(公告)号：US20060081907A1

公开(公告)日：2006-04-20

申请号：US11290461

申请日：2005-12-01

申请人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Seiichi Mori

发明人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Seiichi Mori

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the nonvolatile semiconductor memory elements comprising a gate insulating film formed on the main surface of the semiconductor substrate, a plurality of floating electrodes formed along a first direction on the gate insulating film, a plurality of grooves formed among the plurality of floating electrodes, groove insulating films filled in the plurality of the grooves, a second conductive type impurity diffusion region formed along a second direction so as to sandwich the floating electrodes, interelectrode insulating films formed along the first direction on the plurality of floating electrodes and the groove insulating films, and control electrodes formed on the interelectrode insulating films.

公开(公告)号：US07786013B2

公开(公告)日：2010-08-31

申请号：US11868164

申请日：2007-10-05

申请人： Hiroaki Tsunoda ,  Masahisa Sonoda

发明人： Hiroaki Tsunoda ,  Masahisa Sonoda

IPC分类号： H01L21/311

CPC分类号： H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： The present invention relates to methods of fabricating semiconductor devices, including forming a trench in a semiconductor substrate by a reactive ion etching (RIE) method with a reactive product of film stack of a carbon film/silicon oxide film/carbon-containing silicon oxide film, the trench having an inner surface; and removing the reactive product, by treating the trench with diluted hydrofluoric acid to remove the carbon film and the silicon oxide film followed by treating the film by a hydrofluoric acid vapor phase cleaning (HFVPC) method to remove the carbon-containing silicon oxide film.

摘要翻译： 本发明涉及制造半导体器件的方法，包括通过反应离子蚀刻（RIE）方法在半导体衬底中形成沟槽，该反应性离子蚀刻法用碳膜/氧化硅膜/含碳氧化硅膜的膜堆叠的反应产物 ，所述沟槽具有内表面; 通过用稀氢氟酸处理沟槽以除去碳膜和氧化硅膜，然后用氢氟酸气相清洗（HFVPC）法处理该膜，除去含碳氧化物膜，除去反应产物。

公开(公告)号：US20050040439A1

公开(公告)日：2005-02-24

申请号：US10948661

申请日：2004-09-24

申请人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Eiji Sakagami ,  Hidemi Kanetaka ,  Kenji Matsuzaki ,  Takanori Matsumoto

发明人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Eiji Sakagami ,  Hidemi Kanetaka ,  Kenji Matsuzaki ,  Takanori Matsumoto

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/148

CPC分类号： H01L21/76232 ,  H01L21/823481 ,  H01L21/823878

摘要： A semiconductor device comprising a semiconductor substrate having a substrate top surface on which a device is to be formed; a gate electrode electrically insulated from said semiconductor substrate by a gate-insulating film; a trench formed through said gate electrode into said semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of said substrate top surface; and a boundary portion which is defined between a side surface of said trench and a bottom surface of said trench; wherein said boundary portion have spherical shapes having a curvature radius not smaller than 80 nm.

摘要翻译： 一种半导体器件，包括具有其上将要形成器件的衬底顶表面的半导体衬底; 通过栅极绝缘膜与所述半导体衬底电绝缘的栅电极; 沟槽，通过所述栅电极形成到所述半导体衬底中，用于将用于形成器件的器件区域与所述衬底顶表面的剩余区域电隔离; 以及限定在所述沟槽的侧表面和所述沟槽的底表面之间的边界部分; 其中所述边界部分具有曲率半径不小于80nm的球形。