公开(公告)号：US08916921B2

公开(公告)日：2014-12-23

申请号：US12705088

申请日：2010-02-12

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki

IPC分类号： H01L29/792 ,  H01L27/115 ,  G11C16/04

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582

摘要： A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness DEOT that satisfies the following relation (1). Dsio2

摘要翻译： 多个第一导电层在垂直方向上以一定间隔L设置，夹在其间的电介质。 设定一定间隔L使得第一电介质具有满足以下关系式（1）的等效氧化物厚度DEOT。 Dsio2

公开(公告)号：US08426976B2

公开(公告)日：2013-04-23

申请号：US12392636

申请日：2009-02-25

申请人： Megumi Ishiduki ,  Hideaki Aochi ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Yasuyuki Matsuoka

发明人： Megumi Ishiduki ,  Hideaki Aochi ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/7926

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：在垂直于衬底的方向上延伸的柱状半导体层; 多个导电层，经由存储层形成在所述柱状半导体层的侧壁处; 以及形成在导电层下方的层间绝缘层。 形成面向柱状半导体层的导电层的侧壁，使得其与柱状半导体层的中心轴的距离在其下部位置比在其上部位置变大。 同时，面对柱状半导体层的层间绝缘层的侧壁形成为倾斜，使得其在柱状半导体层的中心轴线处的距离在其下部位置处比在其上部位置变小。

公开(公告)号：US08426276B2

公开(公告)日：2013-04-23

申请号：US13365600

申请日：2012-02-03

申请人： Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/8234

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：在垂直于衬底的方向上延伸的第一柱状半导体层; 电荷累积层，经由第一气隙形成在第一柱状半导体层上，并积累电荷; 与电荷累积层接触的块绝缘层; 以及与块绝缘层接触的多个第一导电层。

公开(公告)号：US08350314B2

公开(公告)日：2013-01-08

申请号：US12325711

申请日：2008-12-01

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/11582

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising: a columnar semiconductor layer perpendicularly extending toward a substrate; a plurality of conductive layers being formed in parallel to the substrate and including a first space between a sidewall of the columnar semiconductor layers; and characteristic change layer being formed on the sidewall of the columnar semiconductor layer faced to the first space or a sidewall of the conductive layer faced to the first space and changing characteristics accompanying with applied voltage; wherein the plurality of the conductive layers have a function of a relative movement to a prescribed direction for the columnar semiconductor layer.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括多个存储器串，每个存储器串由多个电可擦除存储器单元组成，所述多个电可擦除存储器单元串联连接，所述存储器串包括 ：向衬底垂直延伸的柱状半导体层; 多个导电层平行于衬底形成并且包括柱状半导体层的侧壁之间的第一空间; 并且特征变化层形成在面向面向第一空间的导电层的第一空间或侧壁的柱状半导体层的侧壁上，并且伴随施加电压的变化特性; 其中所述多个所述导电层具有对于所述柱状半导体层相对于规定方向的相对移动的功能。

公开(公告)号：US08334561B2

公开(公告)日：2012-12-18

申请号：US12709702

申请日：2010-02-22

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L29/72

CPC分类号： H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11582

摘要： A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.

摘要翻译： 存储器串包括：第一半导体层，具有相对于衬底在垂直方向上延伸的多个柱状部分，以及连接多个柱状部分的下端的接合部分; 围绕所述第一半导体层的侧表面的电荷存储层; 以及围绕电荷存储层的侧表面并用作存储单元的控制电极的第一导电层。 选择晶体管包括：从柱状部分的上表面向上延伸的第二半导体层; 围绕所述第二半导体层的侧表面的绝缘层; 围绕所述绝缘层的侧表面并用作所述选择晶体管的控制电极的第二导电层; 以及形成在所述第二半导体层的上表面上并且包括硅锗的第三半导体层。

公开(公告)号：US08334551B2

公开(公告)日：2012-12-18

申请号：US13120987

申请日：2009-08-25

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

摘要翻译： 每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。 对于每个存储块，存储器串按第二方向布置有m列。 布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。 满足式（1）所示的关系：（式1）m> = n

公开(公告)号：US08330216B2

公开(公告)日：2012-12-11

申请号：US12345088

申请日：2008-12-29

申请人： Yosuke Komori ,  Masaru Kito ,  Megumi Ishiduki ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Yosuke Komori ,  Masaru Kito ,  Megumi Ishiduki ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/66

CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/7926

摘要： A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.

摘要翻译： 非挥发性半导体存储器件包括第一柱状半导体层和形成为使得用于存储电荷的电荷存储层夹在第一导电层和第一柱状半导体层之间的多个第一导电层。 此外，非挥发性半导体存储器件包括第二柱状半导体层和形成为使得绝缘层夹在第二导电层和第二柱状半导体层之间的第二导电层，第二导电层重复地设置在一行中 通过在与层叠方向垂直的第一方向上设置一定间隔来形成。 沿着第二导电层的纵向方向在侧壁上形成与第二导电层接触并沿第一方向延伸的第一侧壁导电层。

公开(公告)号：US08274108B2

公开(公告)日：2012-09-25

申请号：US12705231

申请日：2010-02-12

申请人： Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠体，包括交替层叠有多个电极膜的多个绝缘膜，所述电极膜被分割以形成沿第一方向排列的多个控制栅电极; 多个半导体柱沿堆叠体的堆叠方向排列，半导体柱沿着第一方向以矩阵构造排列，第二方向与第一方向相交以刺穿控制栅电极; 以及将所述半导体柱之一的下端部连接到所述半导体柱的另一个的下端部的连接部件，所述一个半导体柱的上端部与源极线连接，上端部 另一个半导体柱被连接到位线。 至少一些控制栅极电极在第二方向上被彼此相邻的两个半导体柱刺穿。 通过连接构件彼此连接的两个半导体柱穿透彼此不同的控制栅电极。

公开(公告)号：US08084807B2

公开(公告)日：2011-12-27

申请号：US12535847

申请日：2009-08-05

申请人： Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.

摘要翻译： 通过在与硅衬底的上表面正交的方向上交替堆叠用作控制栅极和电介质膜的电极膜来形成多层体。 在多层体中形成在字线方向上延伸的沟槽，并且在沟槽的内表面上形成记忆膜。 随后，将硅体埋在沟槽内，并且电荷存储膜和硅体在字线方向上分开以形成硅柱。 这简化了位线方向上的存储单元的配置，因此可以缩短硅柱的排列间距，减小每个存储单元的面积。

公开(公告)号：US20110284947A1

公开(公告)日：2011-11-24

申请号：US13198359

申请日：2011-08-04

申请人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。