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    SEMICONDUCTOR DEVICE AND PRODUCING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND PRODUCING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20100207209A1

    公开(公告)日：2010-08-19

    申请号：US12563298

    申请日：2009-09-21

    申请人： Hideki Inokuma

    发明人： Hideki Inokuma

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device having a small parasitic resistance and a high driving current is provided. The semiconductor device includes a fin portion that includes a pair of source/drain regions located on both end sides and a channel region sandwiched between the pair of source/drain regions; films that are formed on both sides in a channel-width direction of the fin portion; a gate electrode that is provided so as to stride across the channel region of the fin portion; a gate insulating film that is interposed between the gate electrode and the channel region; and a stress applying layer that applies a stress to the channel region of the fin portion, an upper surface and side surfaces of the source/drain region being coated with the stress applying layer in the fin portion, a lower end surface of the stress applying layer being in contact with the film with no gap.

    摘要翻译： 提供具有小寄生电阻和高驱动电流的半导体器件。 半导体器件包括鳍部，其包括位于两端侧的一对源极/漏极区域和夹在该对源极/漏极区域之间的沟道区域; 在翅片部分的通道宽度方向上形成在两侧的膜; 栅电极，其设置成跨越所述鳍部的沟道区域; 介于栅电极和沟道区之间的栅极绝缘膜; 以及应力施加层，其对所述翅片部分的所述沟道区域施加应力，所述源极/漏极区域的上表面和侧表面在所述翅片部分中涂覆有所述应力施加层，所述应力施加的下端面 层与膜没有间隙地接触。

    Semiconductor device and a method of manufacturing the same
    6.
    发明授权
    Semiconductor device and a method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US08004010B2

    公开(公告)日：2011-08-23

    申请号：US12035260

    申请日：2008-02-21

    申请人： Hideki Inokuma

    发明人： Hideki Inokuma

    IPC分类号： H01L27/11 ,  H01L29/778 ,  H01L21/336

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

    摘要： In a semiconductor device with a shared contact, a gate electrode is formed via a gate insulating film on a semiconductor substrate and a sidewall insulating film is formed on both side faces of the gate electrode. At least one of the surface parts of the semiconductor substrate adjacent to both sides of the gate electrode is removed beyond the lower part of the sidewall insulating film and to the underside of the gate electrode. Then, the gate insulating film exposed in the remove part is removed. An impurity-doped semiconductor layer is formed in the part where the semiconductor substrate and the gate insulating film have been removed.

    摘要翻译： 在具有共用接触的半导体器件中，通过半导体衬底上的栅极绝缘膜形成栅电极，并且在栅电极的两个侧面上形成侧壁绝缘膜。 与栅电极的两侧相邻的半导体衬底的表面部分中的至少一个被去除超过侧壁绝缘膜的下部和栅电极的下侧。 然后，去除暴露在去除部分中的栅极绝缘膜。 在去除半导体衬底和栅极绝缘膜的部分中形成杂质掺杂半导体层。

    Method of fabricating semiconductor device having semiconductor elements
    7.
    发明授权
    Method of fabricating semiconductor device having semiconductor elements 失效
    制造具有半导体元件的半导体器件的方法

    公开(公告)号：US07947554B2

    公开(公告)日：2011-05-24

    申请号：US11905302

    申请日：2007-09-28

    申请人： Hideki Inokuma

    发明人： Hideki Inokuma

    IPC分类号： H01L21/8242 ,  H01L21/20

    CPC分类号： H01L21/823412 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to an aspect of the invention, there is provided a semiconductor device including a first semiconductor element formed on a semiconductor substrate and using electrons as carriers, and a second semiconductor element formed on the semiconductor substrate and using holes as carriers, a first insulating film and a second insulating film formed on source/drain regions and gate electrodes of the first element and the second element, the first insulating film having tensile stress with respect to the first element, and the second insulating film having compression stress with respect to the second element, and sidewall spacers of the gate electrodes of the first element and the second element, at least portions of the sidewall spacers being removed, wherein at least one of the first insulating film and the second insulating film does not close a spacing between the gate electrodes of the first element and the second element.

    摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括形成在半导体衬底上并使用电子作为载体的第一半导体元件和形成在半导体衬底上并使用空穴作为载流子的第二半导体元件，第一绝缘膜 以及形成在所述第一元件和所述第二元件的源极/漏极区域和栅电极上的第二绝缘膜，所述第一绝缘膜相对于所述第一元件具有拉伸应力，并且所述第二绝缘膜相对于所述第二元件具有压缩应力 第一元件和第二元件的栅电极的元件和侧壁间隔物，至少部分侧壁间隔物被去除，其中第一绝缘膜和第二绝缘膜中的至少一个没有闭合栅极之间的间隔 第一元件和第二元件的电极。

    Nonvolatile memory device and method for manufacturing same
    8.
    发明授权
    Nonvolatile memory device and method for manufacturing same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08822968B2

    公开(公告)日：2014-09-02

    申请号：US13600719

    申请日：2012-08-31

    申请人： Hideki Inokuma

    发明人： Hideki Inokuma

    IPC分类号： H01L29/02

    CPC分类号： H01L27/2481 ,  G11C13/0011 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/085 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/1675

    摘要： According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

    摘要翻译： 根据一个实施例，非易失性存储器件包括第一布线层。 该装置包括与第一布线层相交的第二布线层。 并且该装置包括设置在第一布线层和第二布线层相交的位置处的第一存储层。 并且第一存储层与第一布线层接触，第一布线层是能够向第一存储层提供金属离子的层。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20090283834A1

    公开(公告)日：2009-11-19

    申请号：US12407644

    申请日：2009-03-19

    申请人： Hideki Inokuma

    发明人： Hideki Inokuma

    IPC分类号： H01L27/092 ,  H01L21/8234

    CPC分类号： H01L21/823412 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A MOS semiconductor device including MOSFETs each of which has a gate portion formed on a semiconductor substrate and source/drain regions includes sidewall insulating films formed on the side portions of the gate portions in the gate length direction, alloy layers formed on the source/drain regions, taper adjusting insulating films that are formed on the side portions of the sidewall insulating films and in which a taper angle made between a cross section thereof in the gate length direction and the substrate surface is set smaller than a taper angle made between the sidewall insulating film and the substrate surface, a stress-causing insulating film that applies strains to channels and is formed to cover the gate portions, sidewall insulating films and taper adjusting insulating films, and an interlayer insulating film formed on the stress-causing insulating film.

    摘要翻译： 一种MOS半导体器件，包括各自具有形成在半导体衬底上的栅极部分和源极/漏极区域的MOSFET，包括在栅极长度方向上形成在栅极部分的侧部上的侧壁绝缘膜，形成在源极/漏极 形成在侧壁绝缘膜的侧部上的锥形调节绝缘膜，其中在栅极长度方向的截面与基板表面之间形成的锥角设定为小于侧壁之间形成的锥角 绝缘膜和基板表面，对通道施加应变并形成以覆盖栅极部分，侧壁绝缘膜和锥形调节绝缘膜的应力导致绝缘膜以及形成在应力导致绝缘膜上的层间绝缘膜。