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    Non-volatile semiconductor memory device
    1.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08014202B2

    公开(公告)日：2011-09-06

    申请号：US12489870

    申请日：2009-06-23

    申请人： Masayoshi Nakayama ,  Kazuyuki Kouno ,  Reiji Mochida ,  Hoshihide Haruyama

    发明人： Masayoshi Nakayama ,  Kazuyuki Kouno ,  Reiji Mochida ,  Hoshihide Haruyama

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445

    摘要： In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.

    摘要翻译： 在非易失性半导体存储器件中，抑制了当擦除电压施加步骤被重复执行时施加到位线的电压变化，从而减少了擦除后Vt的变化。 存储器阵列包括以阵列布置的存储器单元，多个字线以及多个位线和主位线。 存储器阵列还包括可存储数据的可用区域和不能存储数据的隔离区域。 提供在可用区域中的每个位线通过选择晶体管连接到相应的主位线。 至少一个主位线不仅连接到可用区域的位线，而且还经由选择晶体管连接到隔离区域的位线。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20100027352A1

    公开(公告)日：2010-02-04

    申请号：US12489870

    申请日：2009-06-23

    申请人： Masayoshi NAKAYAMA ,  Kazuyuki Kouno ,  Reiji Mochida ,  Hoshihide Haruyama

    发明人： Masayoshi NAKAYAMA ,  Kazuyuki Kouno ,  Reiji Mochida ,  Hoshihide Haruyama

    IPC分类号： G11C16/04

    CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445

    摘要： In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.

    摘要翻译： 在非易失性半导体存储器件中，抑制了当擦除电压施加步骤被重复执行时施加到位线的电压变化，从而减少了擦除后Vt的变化。 存储器阵列包括以阵列布置的存储器单元，多个字线以及多个位线和主位线。 存储器阵列还包括可存储数据的可用区域和不能存储数据的隔离区域。 提供在可用区域中的每个位线通过选择晶体管连接到相应的主位线。 至少一个主位线不仅连接到可用区域的位线，而且还经由选择晶体管连接到隔离区域的位线。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07924627B2

    公开(公告)日：2011-04-12

    申请号：US12488867

    申请日：2009-06-22

    申请人： Kazuyuki Kouno ,  Hoshihide Haruyama ,  Masayoshi Nakayama ,  Reiji Mochida

    发明人： Kazuyuki Kouno ,  Hoshihide Haruyama ,  Masayoshi Nakayama ,  Reiji Mochida

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C8/10 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/24

    摘要： In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and drain of the memory cell. The discharge transistors receive mutually independent discharge control signals which are generated and outputted from a DS decoder driver at the respective gates thereof. To the bit line which applies the ground voltage to the memory cell, the ground voltage can be set using the discharge transistor.

    摘要翻译： 在半导体存储器件中，当在编程操作期间将接地电压施加到存储器单元时，抑制由于IR-DROP引起的电压上升。 放电晶体管设置在连接到存储单元的源极和漏极的接地和位线之间。 放电晶体管接收相互独立的放电控制信号，这些放电控制信号在DS解码器驱动器的相应门处产生和输出。 对于将接地电压施加到存储单元的位线，可以使用放电晶体管来设置接地电压。

    Nonvolatile semiconductor memory with virtual ground array
    5.
    发明授权
    Nonvolatile semiconductor memory with virtual ground array 失效
    具有虚拟接地阵列的非易失性半导体存储器

    公开(公告)号：US07408820B2

    公开(公告)日：2008-08-05

    申请号：US11641951

    申请日：2006-12-20

    申请人： Takafumi Maruyama ,  Kazuyuki Kouno ,  Akifumi Kawahara ,  Yasuhiro Tomita

    发明人： Takafumi Maruyama ,  Kazuyuki Kouno ,  Akifumi Kawahara ,  Yasuhiro Tomita

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0491 ,  G11C16/28

    摘要： A nonvolatile semiconductor memory of virtual ground array in which a common connection of the sources and a common connection of the drains of nonvolatile memory cells arranged in rows and columns in a memory cell array are used as bit lines, the nonvolatile memory cells including: a reference cell from which a characteristic used as a reference in a differential readout determination operation is obtained; and a neighbor cell at one side of the reference cell, the neighbor cell sharing one of the source and the drain of the reference cell and being connected to a word line which is connected to the reference cell, wherein the nonvolatile semiconductor memory includes a neighbor cell programming circuit to set the neighbor cell to a programmed state when the word line is activated to set the reference cell to a conduction state, the neighbor cell being kept in a non-conduction state during the programmed state.

    摘要翻译： 虚拟接地阵列的非易失性半导体存储器用作位线，其中源和存储单元阵列中以列和列排列的非易失性存储单元的漏极的公共连接的公共连接用作位线，非易失性存储单元包括： 获得在差分读出确定操作中用作参考的特性的参考单元; 以及在所述参考小区的一侧的相邻小区，所述相邻小区分享所述参考小区的源和漏极之一并且连接到连接到所述参考小区的字线，其中所述非易失性半导体存储器包括邻居 当字线被激活以将参考单元设置为导通状态时，相邻单元在编程状态期间保持在非导通状态，将相邻单元设置为编程状态。

    Nonvolatile semiconductor memory
    6.
    发明申请
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US20070183240A1

    公开(公告)日：2007-08-09

    申请号：US11641951

    申请日：2006-12-20

    申请人： Takafumi Maruyama ,  Kazuyuki Kouno ,  Akifumi Kawahara ,  Yasuhiro Tomita

    发明人： Takafumi Maruyama ,  Kazuyuki Kouno ,  Akifumi Kawahara ,  Yasuhiro Tomita

    IPC分类号： G11C7/02

    CPC分类号： G11C16/0491 ,  G11C16/28

    摘要： A nonvolatile semiconductor memory of virtual ground array in which a common connection of the sources and a common connection of the drains of nonvolatile memory cells arranged in rows and columns in a memory cell array are used as bit lines, the nonvolatile memory cells including: a reference cell from which a characteristic used as a reference in a differential readout determination operation is obtained; and a neighbor cell at one side of the reference cell, the neighbor cell sharing one of the source and the drain of the reference cell and being connected to a word line which is connected to the reference cell, wherein the nonvolatile semiconductor memory includes a neighbor cell programming circuit to set the neighbor cell to a programmed state when the word line is activated to set the reference cell to a conduction state, the neighbor cell being kept in a non-conduction state during the programmed state.

    摘要翻译： 虚拟接地阵列的非易失性半导体存储器用作位线，其中源和存储单元阵列中以列和列排列的非易失性存储单元的漏极的公共连接的公共连接用作位线，非易失性存储单元包括： 获得在差分读出确定操作中用作参考的特性的参考单元; 以及在所述参考小区的一侧的相邻小区，所述相邻小区分享所述参考小区的源和漏极之一并且连接到连接到所述参考小区的字线，其中所述非易失性半导体存储器包括邻居 当字线被激活以将参考单元设置为导通状态时，相邻单元在编程状态期间保持在非导通状态，将相邻单元设置为编程状态。

    Regulator circuit
    7.
    发明申请
    Regulator circuit 失效
    调节器电路

    公开(公告)号：US20060119421A1

    公开(公告)日：2006-06-08

    申请号：US11272807

    申请日：2005-11-15

    申请人： Kazuyuki Kouno ,  Norio Hattori

    发明人： Kazuyuki Kouno ,  Norio Hattori

    IPC分类号： G05F1/10

    CPC分类号： G05F1/56

    摘要： A regulator circuit includes: a detection circuit, for outputting a feedback voltage in accordance with an output voltage; a reference voltage input section; a feedback voltage input section; an operational amplification circuit, for comparing a reference voltage and the feedback voltage and outputting a voltage as a comparison result; an output circuit, for supplying an output voltage in accordance with the output of the operational amplification circuit; a connection/disconnection circuit, for connecting or disconnecting the output terminal of the detection circuit and the feedback voltage input section; and a voltage setup circuit, for setting for the feedback voltage input section a predetermined voltage. In the standby state, the connection/disconnection circuit disconnects the output terminal of the detection circuit from the feedback voltage input section, and the voltage setup circuit sets a predetermined voltage for the feedback input section.

    摘要翻译： 调节器电路包括：检测电路，用于根据输出电压输出反馈电压; 基准电压输入部; 反馈电压输入部; 用于比较参考电压和反馈电压并输出电压作为比较结果的运算放大电路; 输出电路，用于根据所述运算放大电路的输出提供输出电压; 连接/断开电路，用于连接或断开检测电路的输出端和反馈电压输入部分; 以及用于将反馈电压输入部分设定为预定电压的电压设置电路。 在待机状态下，连接/断开电路将检测电路的输出端与反馈电压输入部分断开，并且电压建立电路为反馈输入部分设定预定的电压。

    Regulator circuit
    8.
    发明授权
    Regulator circuit 失效
    调节器电路

    公开(公告)号：US07439798B2

    公开(公告)日：2008-10-21

    申请号：US11272807

    申请日：2005-11-15

    申请人： Kazuyuki Kouno ,  Norio Hattori

    发明人： Kazuyuki Kouno ,  Norio Hattori

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： G05F1/56

    摘要： A regulator circuit includes: a detection circuit, for outputting a feedback voltage in accordance with an output voltage; a reference voltage input section; a feedback voltage input section; an operational amplification circuit, for comparing a reference voltage and the feedback voltage and outputting a voltage as a comparison result; an output circuit, for supplying an output voltage in accordance with the output of the operational amplification circuit; a connection/disconnection circuit, for connecting or disconnecting the output terminal of the detection circuit and the feedback voltage input section; and a voltage setup circuit, for setting for the feedback voltage input section a predetermined voltage. In the standby state, the connection/disconnection circuit disconnects the output terminal of the detection circuit from the feedback voltage input section, and the voltage setup circuit sets a predetermined voltage for the feedback input section.

    摘要翻译： 调节器电路包括：检测电路，用于根据输出电压输出反馈电压; 基准电压输入部; 反馈电压输入部; 用于比较参考电压和反馈电压并输出电压作为比较结果的运算放大电路; 输出电路，用于根据所述运算放大电路的输出提供输出电压; 连接/断开电路，用于连接或断开检测电路的输出端和反馈电压输入部分; 以及用于将反馈电压输入部分设定为预定电压的电压设置电路。 在待机状态下，连接/断开电路将检测电路的输出端与反馈电压输入部分断开，并且电压建立电路为反馈输入部分设定预定的电压。

    Non-volatile semiconductor memory device and writing method therefor
    9.
    发明授权
    Non-volatile semiconductor memory device and writing method therefor 有权
    非易失性半导体存储器件及其写入方法

    公开(公告)号：US07260016B2

    公开(公告)日：2007-08-21

    申请号：US11085575

    申请日：2005-03-22

    申请人： Kazuyuki Kouno

    发明人： Kazuyuki Kouno

    IPC分类号： G11C16/24

    CPC分类号： G11C29/36 ,  G11C16/04 ,  G11C16/3454 ,  G11C2029/3602

    摘要： To provide a non-volatile semiconductor memory device which can increase the speed of a writing operation of a physical checker pattern, a logical checker pattern, etc. carried out in an inspection process.First group writing circuits 30a, 30c connected to even-numbered bit lines BL0, BL2 and second group writing circuits 30b, 30d connected to odd-numbered bit lines BL1, BL3 are controlled to an active state and a non-active state respectively on the basis of control signals TSE, TSO. The writing operation of the physical checker pattern is carried out by a program operation for a first page which is carried out while a first word and the first group writing circuits are set to the active state, a program operation for a second page which is carried out while a second word line and the second group writing circuits are set to the active state, and a simultaneous verify operation of the first and second pages which is carried out while the first and second word lines and all the writing circuits are set to the active state.

    摘要翻译： 提供一种可以提高在检查过程中执行的物理检查图案，逻辑检查图案等的写入操作的速度的非易失性半导体存储器件。 连接到偶数位线BL 0，BL 2的第一组写入电路30a，连接到奇数位线BL 1，BL 3的第二组写入电路30b，30d被控制为有效状态， 分别基于控制信号TSE，TSO的非有效状态。 物理检查器图案的写入操作通过在第一个字和第一个组写入电路被设置为活动状态的同时执行的第一页的程序操作来执行，该第二页被携带的第二页的程序操作 在第二字线和第二组写入电路被设置为有效状态的同时，在第一和第二字线和所有写入电路被设置为第一和第二页面的同时验证操作中执行第一和第二页面 活跃状态

    ENGINE START CONTROL SYSTEM FOR HYBRID VEHICLE
    10.
    发明申请
    ENGINE START CONTROL SYSTEM FOR HYBRID VEHICLE 有权
    混合动力车起动控制系统

    公开(公告)号：US20080228363A1

    公开(公告)日：2008-09-18

    申请号：US12034268

    申请日：2008-02-20

    申请人： Kazuyuki Kouno ,  Tomoyuki Kodawara

    发明人： Kazuyuki Kouno ,  Tomoyuki Kodawara

    IPC分类号： G06F17/00

    CPC分类号： B60W10/11 ,  B60K6/48 ,  B60L11/14 ,  B60L2240/421 ,  B60L2240/423 ,  B60L2240/486 ,  B60W10/06 ,  B60W10/08 ,  B60W20/30 ,  B60W30/192 ,  B60W2510/081 ,  B60W2510/1005 ,  B60W2520/10 ,  B60W2540/10 ,  B60W2540/106 ,  B60W2710/083 ,  Y02T10/48 ,  Y02T10/6221 ,  Y02T10/6286 ,  Y02T10/642 ,  Y02T10/70 ,  Y02T10/7077 ,  Y10T477/26 ,  Y10T477/79

    摘要： An engine start control system for starting the engine of a hybrid vehicle operated in an EV drive mode. The system responds quickly to an acceleration request while limiting unpleasant deceleration sensations. The hybrid vehicle has a first clutch disposed between the engine and motor/generator. An electric drive mode exists in which the first clutch is disengaged and the driving torque is provided only by the motor/generator, and a hybrid drive mode exists in which the first clutch is engaged and the driving torque is provided by both the engine and motor/generator. The system uses an engine start shift pattern that is high-geared as compared with a normal shift pattern. Shift control of the transmission is performed using the engine start shift pattern when an engine start request arises. The engine is started by controlling the engagement of the first clutch after performing the shift control.

    摘要翻译： 一种用于启动以EV驱动模式操作的混合动力车辆的发动机的发动机起动控制系统。 系统快速响应加速请求，同时限制令人不快的减速感。 混合动力车辆具有设置在发动机和马达/发电机之间的第一离合器。 存在电动驱动模式，其中第一离合器分离并且仅由电动机/发电机提供驱动转矩，并且存在混合动力模式，其中第一离合器接合并且由发动机和电动机都提供驱动转矩 /发电机。 该系统使用与正常换档模式相比较高齿轮的发动机起动换档模式。 当发动机启动请求出现时，使用发动机起动换档模式进行变速器的换档控制。 通过在执行换档控制之后控制第一离合器的接合来启动发动机。