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12 条记录 (耗时 0.017 秒)

    Comparator
    1.
    发明申请
    Comparator 审中-公开
    比较器

    公开(公告)号：US20080136460A1

    公开(公告)日：2008-06-12

    申请号：US11952214

    申请日：2007-12-07

    申请人： Masayu Fujiwara ,  Kenya Nakamura

    发明人： Masayu Fujiwara ,  Kenya Nakamura

    IPC分类号： H03K5/22

    CPC分类号： H03K5/003 ,  H03K5/24

    摘要： A comparator has: an offset setting portion adapted to set an offset voltage; an offset subtracting portion adapted to subtract the offset voltage from a non-inverting input voltage; and a comparing portion adapted to shift the output logic level thereof according to which of the output voltage of the offset subtracting portion and an inverting input voltage is higher.

    摘要翻译： 比较器具有：偏移设定部分，用于设定偏移电压; 偏移减去部分，适于从非反相输入电压中减去所述偏移电压; 以及比较部分，其适于根据偏移减去部分的输出电压和反相输入电压中的哪一个偏移其输出逻辑电平。

    Clock generation system
    3.
    发明授权
    Clock generation system 有权
    时钟发生系统

    公开(公告)号：US07216249B2

    公开(公告)日：2007-05-08

    申请号：US10457149

    申请日：2003-06-09

    申请人： Masayu Fujiwara ,  Masaki Onishi

    发明人： Masayu Fujiwara ,  Masaki Onishi

    IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  H03L7/16 ,  H03L7/18 ,  H03B19/12 ,  H03K3/03 ,  H03K21/00 ,  H03K23/00

    CPC分类号： H03L7/23 ,  G06F1/06 ,  G11B20/1403

    摘要： A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

    摘要翻译： 一种时钟发生系统，用于使用PL电路产生具有与参考时钟的参考频率具有预定比率的各个频率的第一，第二和第三参考频率时钟，使得时钟具有足够的S / 尽管S / N比受到本底噪声的限制，N比也是如此。 第一参考频率时钟被提供给第一PLL电路以产生具有与参考时钟具有预定比率的中频的中频时钟。 中频时钟被提供给第二和第三PLL电路，以分别产生具有分别具有与中频的第二和第三比率的频率的第二和第三参考频率时钟。

    Semiconductor device, a method of improving a distortion of an output waveform, and an electronic apparatus
    4.
    发明授权
    Semiconductor device, a method of improving a distortion of an output waveform, and an electronic apparatus 有权
    半导体器件，改善输出波形的失真的方法以及电子设备

    公开(公告)号：US08653875B2

    公开(公告)日：2014-02-18

    申请号：US13432097

    申请日：2012-03-28

    申请人： Morihiko Tokumoto ,  Masayu Fujiwara ,  Satoshi Mikami

    发明人： Morihiko Tokumoto ,  Masayu Fujiwara ,  Satoshi Mikami

    IPC分类号： H03H11/26

    CPC分类号： H03K5/1508 ,  H03K19/00369

    摘要： Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure.

    摘要翻译： 提供一种输入预定频率的输入时钟信号并输出​​相同频率的多个时钟信号的半导体器件，所述半导体器件包括：输入单元，被配置为输入预定频率的输入时钟信号; 以及延迟单元，被配置为通过为要延迟的输入时钟信号提供预定的延迟时间周期来产生相同频率的多个时钟信号，以便减少与多个时钟信号相同的施加到电源的负载。 根据半导体器件，即使结构简单，也可以提高时钟信号的输出波形失真。

    Clock Input/Output Device
    6.
    发明申请
    Clock Input/Output Device 审中-公开
    时钟输入/输出设备

    公开(公告)号：US20080143410A1

    公开(公告)日：2008-06-19

    申请号：US10566914

    申请日：2004-08-04

    申请人： Masaki Onishi ,  Masayu Fujiwara

    发明人： Masaki Onishi ,  Masayu Fujiwara

    IPC分类号： H03K3/02

    CPC分类号： H03K19/00323 ,  H03K5/1565 ,  H03K19/09429 ,  H03K19/0948 ,  H03K2005/00136

    摘要： A clock input/output device has three-state inverters Iv1 to Iv3 and an inverter Iv4, which cooperate to make equal the on-state resistance through a supply-voltage-side (VDD-side) transistor and the on-state resistance through a ground-voltage-side (0-side) transistor so as to make equal to VDD/2 the threshold voltage with reference to which the clock input/output device evaluates the input thereto to determine whether or not to change the state of the output thereof.

    摘要翻译： 时钟输入/输出装置具有三态反相器Iv 1至Iv 3和反相器Iv 4，它们协作以使得通过电源电压侧（VDD侧）晶体管等于导通状态电阻和导通状态 通过接地电压侧（0侧）晶体管的电阻以使得等于VDD / 2的阈值电压，参考时钟输入/输出装置对其输入进行评估，以确定是否改变 其输出。

    Method of generating a clock, a clock generation device, and electronic apparatuses having a clock generation device
    7.
    发明授权
    Method of generating a clock, a clock generation device, and electronic apparatuses having a clock generation device 失效
    时钟生成方法，时钟生成装置以及具有时钟生成装置的电子装置

    公开(公告)号：US06727773B2

    公开(公告)日：2004-04-27

    申请号：US10145241

    申请日：2002-05-13

    申请人： Masayu Fujiwara

    发明人： Masayu Fujiwara

    IPC分类号： H03C306

    CPC分类号： H03L7/197 ,  H03K3/0231 ,  H03K4/502 ,  H03L7/18 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/067

    摘要： In generating a frequency-modulated clock, a first frequency modulation (FM) signal having frequency fm1 is frequency-modulated by a second FM signal having a second frequency fm2, generating a clock modulation signal fm0. The clock generation signal fm0 is used to frequency-modulate the system clock CLK by the clock modulation signal fm0. Thus, the spectrum of the clock is doubly dispersed by the first and the second FM frequencies. As a result, peak levels at the fundamental and higher harmonic frequencies are reduced as compared with conventional clock generation device.

    摘要翻译： 在产生调频时钟时，具有频率fm1的第一频率调制（FM）信号由具有第二频率fm2的第二FM信号进行频率调制，产生时钟调制信号fm0。 时钟产生信号fm0用于通过时钟调制信号fm0对系统时钟CLK进行频率调制。 因此，时钟的频谱被第一和第二FM频率双重分散。 结果，与传统的时钟发生装置相比，基波和高次谐波频率的峰值电平降低。

    Constant voltage output device
    8.
    发明授权
    Constant voltage output device 失效
    恒压输出装置

    公开(公告)号：US6091285A

    公开(公告)日：2000-07-18

    申请号：US988468

    申请日：1997-12-10

    申请人： Masayu Fujiwara

    发明人： Masayu Fujiwara

    IPC分类号： G05F3/24 ,  G05F3/30 ,  G06F3/02

    CPC分类号： G05F3/30

    摘要： A constant voltage output device has a field-effect transistor and a comparator. Between the output electrode of the field-effect transistor and ground, a first resistor, a second resistor, and a first diode are connected in series. Moreover, between the output electrode of the field-effect transistor and ground, a third resistor and a second diode are connected in series. The comparator compares the voltage at the node between the first and second resistors with the voltage at the node between the third resistor and the second diode, and feeds the comparison result to the gate of the field-effect transistor. At an output terminal appears a desired voltage that is determined by the ratio between the current capacities of the first and second diodes and by the ratio between the resistances of the first and second resistors.

    摘要翻译： 恒压输出装置具有场效应晶体管和比较器。 在场效应晶体管的输出电极和地之间，串联连接有第一电阻器，第二电阻器和第一二极管。 此外，在场效应晶体管的输出电极和地之间，串联连接有第三电阻器和第二二极管。 比较器将第一和第二电阻之间的节点处的电压与第三电阻器和第二二极管之间的节点处的电压进行比较，并将比较结果馈送到场效应晶体管的栅极。 在输出端子出现由第一和第二二极管的电流容量与第一和第二电阻器的电阻之间的比率确定的期望电压。

    Clock generation system
    10.
    发明授权
    Clock generation system 失效
    时钟发生系统

    公开(公告)号：US07084712B2

    公开(公告)日：2006-08-01

    申请号：US10919634

    申请日：2004-08-17

    申请人： Masayu Fujiwara

    发明人： Masayu Fujiwara

    IPC分类号： H03B19/12 ,  H03K3/03 ,  H03K21/00 ,  H03K23/00 ,  H03L7/00

    CPC分类号： H03L7/1974 ,  H03L7/23

    摘要： A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.

    摘要翻译： 提供了分频参考频率时钟作为相位比较器的参考输入。 具有与另一参考频率时钟相关联的频率的可控振荡器的振荡频率信号由分频因子切换型比较输入分频电路进行频率分频。 所得到的分频时钟作为比较输入提供给相位比较器。 比较输入分频电路的分频因子基于分频因子控制信号从一个切换到另一个，以产生相对于另一参考频率时钟具有预定频率比的振荡频率信号。 因此，以足够的S / N比获得符合MPEG格式的27MHz，33.8688MHz和36.864MHz的三个参考频率时钟。