公开(公告)号：US06795050B1

公开(公告)日：2004-09-21

申请号：US09383923

申请日：1999-08-26

申请人： Masumitsu Ino ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

发明人： Masumitsu Ino ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2310/0297 ,  G09G2320/0209

摘要： An active-matrix-type liquid crystal display device supplies signal potentials to signal lines of a liquid crystal display panel according to a time-division drive method using time-division switches. The low-level potential of select pulses to be supplied from a select pulse generating circuit to CMOS analog switches of the time-division switches is set to be lower than the low-level potential of a signal potential output from a horizontal drive circuit. With this arrangement, even if the signal potential of a non-selected signal line is decreased due to the crosstalk of a signal potential from a selected signal line to the non-selected signal line, the generation of insufficient contrast and non-uniformity of the luminance in the horizontal direction can be prevented. As a consequence, a high image quality is maintained.

摘要翻译： 根据使用时分开关的时分驱动方法，有源矩阵型液晶显示装置向液晶显示面板的信号线提供信号电位。 将从选择脉冲发生电路提供的选择脉冲的低电平电位设置为低于从水平驱动电路输出的信号电位的低电位电位。 利用这种布置，即使由于从所选择的信号线到未选择的信号线的信号电位的串扰，未被选择的信号线的信号电位降低，产生不足的对比度和不均匀性 可以防止水平方向的亮度。 因此，保持高图像质量。

公开(公告)号：US06424328B1

公开(公告)日：2002-07-23

申请号：US09271211

申请日：1999-03-17

申请人： Masumitsu Ino ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

发明人： Masumitsu Ino ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

IPC分类号： G09G330

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0876 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2320/0247

摘要： When time-division driving, which allows the number of output pins of a driver IC to be reduced, is applied to an active-matrix LCD apparatus, a time-division number is set to an odd number, preferably to the n-th (n: natural number) power of three, and a time-sequential signal (dot inversion signal) output from the driver IC is time-divided by a time-division switch and sent to signal lines 12-1, 12-2, 12-3, . . . to implement complete dot inversion driving.

摘要翻译： 当将有助于减少驱动器IC的输出引脚数的时分驱动应用于有源矩阵LCD装置时，将时分数设定为奇数，最好设定为第n（ n：自然数）三次的功率和从驱动器IC输出的时间顺序信号（点反转信号）通过时分开关进行时分，并发送到信号线12-1,12-2,12- 3，。 。 。 实现完整的点反转驱动。

公开(公告)号：US20120162161A1

公开(公告)日：2012-06-28

申请号：US13417991

申请日：2012-03-12

申请人： Masumitsu Ino ,  Hiroyoshi Tsubota ,  Hiroaki Ichikawa ,  Shinichi Teraguchi ,  Taketo Oka ,  Toru Akutagawa ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Naoshi Goto

发明人： Masumitsu Ino ,  Hiroyoshi Tsubota ,  Hiroaki Ichikawa ,  Shinichi Teraguchi ,  Taketo Oka ,  Toru Akutagawa ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Naoshi Goto

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/3688 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2330/021

摘要： A liquid crystal display having: a liquid crystal display panel in which a plurality of pixels are two-dimensionally arranged at intersecting points of gate lines as many as a plurality of rows and signal lines as many as a plurality of columns which are wired in a matrix shape; and a plurality of driver ICs for applying a signal potential to each pixel of the liquid crystal display panel through the signal lines of a plurality of columns, wherein the number of output pins of each of a plurality of driver ICs is set to the measure of the total number of signal lines of a plurality of columns, thereby preventing that a fraction occurs in the signal lines.

摘要翻译： 一种液晶显示器，具有：液晶显示面板，其中多个像素被二维布置在多条行的栅极线的交点处，多条像多条列的信号线布线在 矩阵形状 以及多个驱动器IC，用于通过多个列的信号线向液晶显示面板的每个像素施加信号电位，其中多个驱动器IC中的每一个的输出引脚的数量被设置为 多个列的信号线的总数，从而防止在信号线中发生分数。

公开(公告)号：US20080136810A1

公开(公告)日：2008-06-12

申请号：US10568538

申请日：2004-08-20

申请人： Naoyuki Itakura ,  Hiroaki Ichikawa ,  Toshikazu Maekawa

发明人： Naoyuki Itakura ,  Hiroaki Ichikawa ,  Toshikazu Maekawa

IPC分类号： G06F3/038

CPC分类号： G09G3/2011 ,  G09G3/2074 ,  G09G3/3607 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0251 ,  G09G2310/0297 ,  G09G2320/0223

摘要： In the present invention, during a 1H period excluding a blanking period (1HB) constituting a line display period, pixel data pulses of RGB (61B to 61R) are successively supplied for each color to corresponding signal lines for color display of one pixel line. A control circuit (40) of select switches connected to the signal lines (6-1 to 6-n) supplies permission pulses (63B to 63R) for supply of data to signal lines when displaying one color among RGB to select switches (TMG), and turns on the select switch (TMG) of the signal line corresponding to another color to be displayed later in the same line display period during the period of this application by a precharge pulse (62G or 62R) having a time duration shorter than the supply time of the pixel data of the other color (T2 or T3) to previously precharge the signal line of the other color to the predetermined potential. Due to this, sufficient precharging of a signal line which became difficult due to an increase of a load capacitance of the signal line due to higher definition of the image display device and increase in speed of a drive clock thereof can be achieved.

摘要翻译： 在本发明中，除了构成行显示期间的消隐期间（1HB）以外的1HH期间内，依次向每个颜色的RGB（61B〜61R）的像素数据脉冲供给相应的信号线， 一个像素线。 连接到信号线（6-1至6-n）的选择开关的控制电路（40）提供允许脉冲（63B至63R），用于在RGB之间显示一种颜色以选择开关时向信号线提供数据 TMG），并且在该应用期间，在具有时间的预充电脉冲（62G或62R）的同一行显示周期中，打开与其他颜色对应的信号线的选择开关（TMG） 持续时间短于其他颜色（T 2或T 3）的像素数据的供给时间，以预先将另一种颜色的信号线预充电到预定电位。 由此，可以实现由于图像显示装置的高清晰度和驱动时钟的速度的增加而导致由于信号线的负载电容的增加而变得困难的信号线的充分的预充电。

公开(公告)号：US5448384A

公开(公告)日：1995-09-05

申请号：US172272

申请日：1993-12-23

申请人： Katsuhide Uchino ,  Toshikazu Maekawa ,  Hiroaki Ichikawa

发明人： Katsuhide Uchino ,  Toshikazu Maekawa ,  Hiroaki Ichikawa

IPC分类号： G02F1/133 ,  G02F1/1345 ,  G02F1/136 ,  G02F1/1368 ,  G09G3/36 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2310/0245 ,  G09G2310/063 ,  G09G2320/0204 ,  G09G2320/0219 ,  G09G2330/04

摘要： A liquid crystal display device of the active matrix type which prevents residual of charge in liquid crystal picture elements with respect to time. The active matrix liquid crystal display device includes liquid crystal picture elements formed from a liquid crystal layer held between picture element electrodes arranged in a matrix and common electrodes opposing to the picture element electrodes, and picture element transistors corresponding to the liquid crystal picture elements. While a predetermined reference potential is supplied to the common electrode, image signals are applied to the individual picture element electrodes by way of signal lines and picture element transistors to effect ac driving of the liquid crystal picture elements. Discharge means for connecting the common electrodes and the picture element electrodes to an equivalent potential to each other is provided to discharge the charge remaining in the liquid crystal picture elements thereby to prevent the variation of the reference potential.

摘要翻译： 一种有源矩阵型的液晶显示装置，其防止相对于时间在液晶像素中残留电荷。 有源矩阵液晶显示装置包括由保持在矩阵中排列的像素电极和与像素电极相对的公共电极之间的液晶层形成的液晶像元，以及与液晶像素相对应的像素晶体管。 当向公共电极提供预定的参考电位时，通过信号线和像素晶体管将图像信号施加到各个像素电极，以实现液晶图像元件的交流驱动。 设置用于将公共电极和像素电极彼此连接的等效电位的放电装置，以排出残留在液晶像素中的电荷，从而防止参考电位的变化。

公开(公告)号：US07773084B2

公开(公告)日：2010-08-10

申请号：US10568538

申请日：2004-08-20

申请人： Naoyuki Itakura ,  Hiroaki Ichikawa ,  Toshikazu Maekawa

发明人： Naoyuki Itakura ,  Hiroaki Ichikawa ,  Toshikazu Maekawa

IPC分类号： G06G3/038

CPC分类号： G09G3/2011 ,  G09G3/2074 ,  G09G3/3607 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0251 ,  G09G2310/0297 ,  G09G2320/0223

摘要： In the present invention, during an 1H period excluding a blanking period (1HB) constituting a line display period, pixel data pulses of RGB (61B to 61R) are successively supplied for each color to corresponding signal lines for the color display of one pixel line. A control circuit (40) of select switches connected to the signal lines (6-1 to 6-n) supplies permission pulses (63B to 63R) for the supply of data to signal lines when displaying one color among RGB to select switches (TMG), and turns on the select switch (TMG) of the signal line corresponding to another color to be displayed later in the same line display period during the period of this application by a precharge pulse (62G or 62R) having a time duration shorter than the supply time of the pixel data of the other color (T2 or T3) to previously precharge the signal line of the other color to the predetermined potential. Due to this, sufficient precharging of a signal line, which became difficult due to an increase of a load capacitance of the signal line due to higher definition of the image display device and an increase in the speed of a drive clock thereof, can be achieved.

摘要翻译： 在本发明中，除了构成行显示期间的消隐期间（1HB）以外的1H期间内，依次向每个颜色的像素数据脉冲供给各色用于一个像素线的彩色显示的相应信号线 。 连接到信号线（6-1至6-n）的选择开关的控制电路（40）提供允许脉冲（63B至63R），用于在RGB之间显示一种颜色以选择开关（TMG ），并且在该应用期间的相同行显示周期中，通过具有时间短于的持续时间的预充电脉冲（62G或62R），打开与其他颜色相对应的信号线的选择开关（TMG） 其他颜色（T2或T3）的像素数据的供给时间预先将另一种颜色的信号线预充电到预定电位。 由此，可以实现由于图像显示装置的更高清晰度而导致的由于信号线的负载电容的增加而导致的信号线的充分的预充电以及其驱动时钟的速度的增加。 。

公开(公告)号：US20050270080A1

公开(公告)日：2005-12-08

申请号：US11171172

申请日：2005-06-28

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/086

CPC分类号： G09G3/3688 ,  G09G3/3655 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0294 ,  H03K3/356165

摘要： In the structure in which an input signal IN and a reverse-phase signal XIN thereof are externally input, an external IC is required for generating the reverse-phase signal XIN, and the number of required input signal terminals is two. A level shift circuit formed on an insulating substrate, such as a glass substrate, using transistors with large characteristic variations, for example, TFTs with high thresholds Vth, includes a complementary generator unit (11) driven by a first power supply (VCC) having an amplitude voltage equal to the amplitude voltage of a signal externally input from the substrate to generate complementary signals from a single-phase input signal IN. The complementary signals generated by the complementary generator unit (11) are level-shifted by a level shift unit (14). Therefore, it is no longer necessary to externally input the reverse-phase signal XIN.

摘要翻译： 在外部输入输入信号IN和反相信号XIN的结构中，需要外部IC来产生反相信号XIN，所需输入信号端子数为2。 使用具有大特性变化的晶体管等绝缘基板（例如玻璃基板）形成的电平移动电路，例如具有高阈值Vth的TFT，包括由第一电源（VCC）驱动的互补发电单元（11），第一电源（VCC） 幅度电压等于从衬底外部输入的信号的幅度电压，以产生来自单相输入信号IN的互补信号。 由互补发生器单元（11）产生的互补信号由电平移位单元（14）进行电平移位。 因此，不再需要外部输入反相信号XIN。

公开(公告)号：US20060012557A1

公开(公告)日：2006-01-19

申请号：US11207352

申请日：2005-08-19

申请人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

发明人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G02F1/13394 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2330/021

摘要： When a data processing circuit is formed on an insulating substrate by using TFTs, it is difficult to process a data signal having a high data rate, such as digital display data, at a high speed. In a data processing circuit formed on an insulating substrate by using TFTs, a data signal having a small voltage amplitude input in series is increased in level to a data signal having a large voltage amplitude by a level shift circuit (11), the serial data signal having the large voltage amplitude is converted to parallel data signals by a serial-parallel conversion circuit (12), and then, the parallel data signals are reduced in level to data signals having a small voltage amplitude by level shift circuits (13A and 13B). Therefore, high-speed processing can be applied to digital data signals at a low power consumption.

摘要翻译： 当通过使用TFT在绝缘基板上形成数据处理电路时，难以高速处理诸如数字显示数据的数据速率高的数据信号。 在通过使用TFT形成在绝缘基板上的数据处理电路中，串联输入的电压振幅小的数据信号通过电平移位电路（11）增加到电压振幅较大的数据信号，串行数据 具有大电压幅度的信号通过串行 - 并行转换电路（12）被转换为并行数据信号，然后并行数据信号通过电平移位电路（13A和 13 B）。 因此，可以以低功耗将高速处理应用于数字数据信号。

公开(公告)号：US20050024313A1

公开(公告)日：2005-02-03

申请号：US10485293

申请日：2003-05-28

申请人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

发明人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

IPC分类号： G02F1/1343 ,  G02F1/133 ,  G02F1/1339 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G02F1/13394 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2330/021

摘要： When a data processing circuit is formed on an insulating substrate by using TFTs, it is difficult to process a data signal having a high data rate, such as digital display data, at a high speed. In a data processing circuit formed on an insulating substrate by using TFTs, a data signal having a small voltage amplitude input in series is increased in level to a data signal having a large voltage amplitude by a level shift circuit (11), the serial data signal having the large voltage amplitude is converted to parallel data signals by a serial-parallel conversion circuit (12), and then, the parallel data signals are reduced in level to data signals having a small voltage amplitude by level shift circuits (13A and 13B). Therefore, high-speed processing can be applied to digital data signals at a low power consumption.

摘要翻译： 当通过使用TFT在绝缘基板上形成数据处理电路时，难以高速处理诸如数字显示数据的数据速率高的数据信号。 在通过使用TFT形成在绝缘基板上的数据处理电路中，串联输入的电压振幅小的数据信号通过电平移位电路（11）增加到电压振幅较大的数据信号，串行数据 具有大电压幅度的信号通过串并转换电路（12）被转换为并行数据信号，然后并行数据信号被电平移位电路（13A和13B）降低到电压振幅较小的数据信号 ）。 因此，可以以低功耗将高速处理应用于数字数据信号。

公开(公告)号：US07564441B2

公开(公告)日：2009-07-21

申请号：US11207352

申请日：2005-08-19

申请人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

发明人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G02F1/13394 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2330/021

摘要： When a data processing circuit is formed on an insulating substrate by using TFTs, it is difficult to process a data signal having a high data rate, such as digital display data, at a high speed.In a data processing circuit formed on an insulating substrate by using TFTs, a data signal having a small voltage amplitude input in series is increased in level to a data signal having a large voltage amplitude by a level shift circuit (11), the serial data signal having the large voltage amplitude is converted to parallel data signals by a serial-parallel conversion circuit (12), and then, the parallel data signals are reduced in level to data signals having a small voltage amplitude by level shift circuits (13A and 13B). Therefore, high-speed processing can be applied to digital data signals at a low power consumption.

摘要翻译： 当通过使用TFT在绝缘基板上形成数据处理电路时，难以高速处理诸如数字显示数据的数据速率高的数据信号。 在通过使用TFT形成在绝缘基板上的数据处理电路中，串联输入的电压振幅小的数据信号通过电平移位电路（11）增加到电压振幅较大的数据信号，串行数据 具有大电压幅度的信号通过串并转换电路（12）被转换为并行数据信号，然后并行数据信号被电平移位电路（13A和13B）降低到电压振幅较小的数据信号 ）。 因此，可以以低功耗将高速处理应用于数字数据信号。