公开(公告)号：US06795050B1

公开(公告)日：2004-09-21

申请号：US09383923

申请日：1999-08-26

申请人： Masumitsu Ino ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

发明人： Masumitsu Ino ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2310/0297 ,  G09G2320/0209

摘要： An active-matrix-type liquid crystal display device supplies signal potentials to signal lines of a liquid crystal display panel according to a time-division drive method using time-division switches. The low-level potential of select pulses to be supplied from a select pulse generating circuit to CMOS analog switches of the time-division switches is set to be lower than the low-level potential of a signal potential output from a horizontal drive circuit. With this arrangement, even if the signal potential of a non-selected signal line is decreased due to the crosstalk of a signal potential from a selected signal line to the non-selected signal line, the generation of insufficient contrast and non-uniformity of the luminance in the horizontal direction can be prevented. As a consequence, a high image quality is maintained.

摘要翻译： 根据使用时分开关的时分驱动方法，有源矩阵型液晶显示装置向液晶显示面板的信号线提供信号电位。 将从选择脉冲发生电路提供的选择脉冲的低电平电位设置为低于从水平驱动电路输出的信号电位的低电位电位。 利用这种布置，即使由于从所选择的信号线到未选择的信号线的信号电位的串扰，未被选择的信号线的信号电位降低，产生不足的对比度和不均匀性 可以防止水平方向的亮度。 因此，保持高图像质量。

公开(公告)号：US06424328B1

公开(公告)日：2002-07-23

申请号：US09271211

申请日：1999-03-17

申请人： Masumitsu Ino ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

发明人： Masumitsu Ino ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

IPC分类号： G09G330

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0876 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2320/0247

摘要： When time-division driving, which allows the number of output pins of a driver IC to be reduced, is applied to an active-matrix LCD apparatus, a time-division number is set to an odd number, preferably to the n-th (n: natural number) power of three, and a time-sequential signal (dot inversion signal) output from the driver IC is time-divided by a time-division switch and sent to signal lines 12-1, 12-2, 12-3, . . . to implement complete dot inversion driving.

摘要翻译： 当将有助于减少驱动器IC的输出引脚数的时分驱动应用于有源矩阵LCD装置时，将时分数设定为奇数，最好设定为第n（ n：自然数）三次的功率和从驱动器IC输出的时间顺序信号（点反转信号）通过时分开关进行时分，并发送到信号线12-1,12-2,12- 3，。 。 。 实现完整的点反转驱动。

公开(公告)号：US20120162161A1

公开(公告)日：2012-06-28

申请号：US13417991

申请日：2012-03-12

申请人： Masumitsu Ino ,  Hiroyoshi Tsubota ,  Hiroaki Ichikawa ,  Shinichi Teraguchi ,  Taketo Oka ,  Toru Akutagawa ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Naoshi Goto

发明人： Masumitsu Ino ,  Hiroyoshi Tsubota ,  Hiroaki Ichikawa ,  Shinichi Teraguchi ,  Taketo Oka ,  Toru Akutagawa ,  Toshikazu Maekawa ,  Yoshiharu Nakajima ,  Naoshi Goto

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/3688 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2330/021

摘要： A liquid crystal display having: a liquid crystal display panel in which a plurality of pixels are two-dimensionally arranged at intersecting points of gate lines as many as a plurality of rows and signal lines as many as a plurality of columns which are wired in a matrix shape; and a plurality of driver ICs for applying a signal potential to each pixel of the liquid crystal display panel through the signal lines of a plurality of columns, wherein the number of output pins of each of a plurality of driver ICs is set to the measure of the total number of signal lines of a plurality of columns, thereby preventing that a fraction occurs in the signal lines.

摘要翻译： 一种液晶显示器，具有：液晶显示面板，其中多个像素被二维布置在多条行的栅极线的交点处，多条像多条列的信号线布线在 矩阵形状 以及多个驱动器IC，用于通过多个列的信号线向液晶显示面板的每个像素施加信号电位，其中多个驱动器IC中的每一个的输出引脚的数量被设置为 多个列的信号线的总数，从而防止在信号线中发生分数。

公开(公告)号：US08466886B2

公开(公告)日：2013-06-18

申请号：US12585316

申请日：2009-09-11

申请人： Hiroshi Mizuhashi ,  Yuko Yamauchi ,  Yoshiharu Nakajima ,  Tsutomu Tanaka ,  Shuji Hayashi ,  Takeo Koito ,  Masumitsu Ino

发明人： Hiroshi Mizuhashi ,  Yuko Yamauchi ,  Yoshiharu Nakajima ,  Tsutomu Tanaka ,  Shuji Hayashi ,  Takeo Koito ,  Masumitsu Ino

IPC分类号： G06F3/041

CPC分类号： G06F3/0412

摘要： A liquid-crystal display panel includes: gate lines each serving as a row-direction line which is one of the rows of a two-dimensional matrix; data signal lines each serving as a column-direction line which is one of the columns of the two-dimensional matrix; a plurality of liquid-crystal pixel sections which are laid out to form the two-dimensional matrix and each placed at the intersection of one of the gate lines and one of the data signal lines; chopper-type comparators each connected to one of the data signal lines and each used for converting the value of a sensor signal read out from one of the liquid-crystal pixel sections connected to the data signal lines into a binary value; and a shift register for converting outputs of the chopper-type comparators from parallel data into serial data and outputting the serial data.

摘要翻译： 液晶显示面板包括：各自用作行方向线的栅极线，其为二维矩阵的行之一; 数据信号线各自用作作为二维矩阵的列之一的列方向线; 多个液晶像素部分，布置成形成二维矩阵，并且各自放置在一条栅极线和一条数据信号线之间的交叉处; 斩波器型比较器，每个连接到数据信号线之一，每个用于将连接到数据信号线的液晶像素部分中读出的传感器信号的值转换为二进制值; 以及用于将斩波型比较器的输出从并行数据转换为串行数据并输出串行数据的移位寄存器。

公开(公告)号：US20100097340A1

公开(公告)日：2010-04-22

申请号：US12585316

申请日：2009-09-11

申请人： Hiroshi Mizuhashi ,  Yuko Yamauchi ,  Yoshiharu Nakajima ,  Tsutomu Tanaka ,  Shuji Hayashi ,  Takeo Koito ,  Masumitsu Ino

发明人： Hiroshi Mizuhashi ,  Yuko Yamauchi ,  Yoshiharu Nakajima ,  Tsutomu Tanaka ,  Shuji Hayashi ,  Takeo Koito ,  Masumitsu Ino

IPC分类号： G06F3/041

CPC分类号： G06F3/0412

摘要： A liquid-crystal display panel includes: gate lines each serving as a row-direction line which is one of the rows of a two-dimensional matrix; data signal lines each serving as a column-direction line which is one of the columns of the two-dimensional matrix; a plurality of liquid-crystal pixel sections which are laid out to form the two-dimensional matrix and each placed at the intersection of one of the gate lines and one of the data signal lines; chopper-type comparators each connected to one of the data signal lines and each used for converting the value of a sensor signal read out from one of the liquid-crystal pixel sections connected to the data signal lines into a binary value; and a shift register for converting outputs of the chopper-type comparators from parallel data into serial data and outputting the serial data.

摘要翻译： 液晶显示面板包括：各自用作行方向线的栅极线，其为二维矩阵的行之一; 数据信号线各自用作作为二维矩阵的列之一的列方向线; 多个液晶像素部分，布置成形成二维矩阵，并且各自放置在一条栅极线和一条数据信号线之间的交叉处; 斩波器型比较器，每个连接到数据信号线之一，每个用于将连接到数据信号线的液晶像素部分中读出的传感器信号的值转换为二进制值; 以及用于将斩波型比较器的输出从并行数据转换为串行数据并输出串行数据的移位寄存器。

公开(公告)号：US08031188B2

公开(公告)日：2011-10-04

申请号：US12081269

申请日：2008-04-14

申请人： Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： G09G5/00

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/06 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28 ,  G11C27/02 ,  H03K3/35613 ,  H03K19/018521 ,  H03M1/76

摘要： A digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels. A level shift circuit in the shift register has a basic structure of CMOS latch cells and is utilized in each level shift of the clock signal at each transfer stage, a sampling latch circuit with a basic structure of CMOS latch cells has a level shift function, and these respective circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated liquid crystal display device to provide an LCD panel with an extremely narrow picture frame, stable level shift operation, stable sampling & latch operation in a circuit structure having an extremely small number of components, low power consumption and a small surface area.

摘要翻译： 数字/模拟转换器电路，电平移位电路，包含该电平移位电路的移位寄存器，采样锁存电路和锁存电路以及安装有这些各自电路的液晶显示装置，其中与 包含数字/模拟转换器电路的LCD装置具有在基板上以矩阵形式排列的多晶硅薄膜晶体管作为用于像素的开关器件。 移位寄存器中的电平移位电路具有CMOS锁存单元的基本结构，并且在每个传输级的时钟信号的每个电平移位中被使用，具有CMOS锁存单元的基本结构的采样锁存电路具有电平移位功能， 并且这些各个电路可以与驱动电路集成液晶显示装置结合到单个扫描型结构电路中，以提供具有极窄图像帧的LCD面板，稳定的电平移位操作，电路结构中的稳定采样和锁存操作 具有极少数量的部件，低功耗和小的表面积。

公开(公告)号：US07932901B2

公开(公告)日：2011-04-26

申请号：US11880699

申请日：2007-07-24

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： G09G5/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2330/021 ,  Y02D10/126

摘要： A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.

摘要翻译： 具有低功耗和小布局区域的定时发生电路，包括作为一个外围驱动电路的定时发生电路的显示装置和包括作为显示输出部分的显示装置的便携式终端。 在形成在绝缘基板上的定时发生电路中，基于主时钟MCK产生具有不同频率的输出脉冲SRFF1out〜SRFFnout，时钟发生电路（11）生成频率低于主时钟MCK的工作时钟 频率。 然后，基于该工作时钟，计数部（12）工作，从移位寄存器（121-1）至（121-m）依次输出移位脉冲S / R1out至S / Rmount。 输出脉冲生成部（13）根据移位脉冲S / R1out〜S / Rmount的组合，生成输出脉冲SF1out〜SFnout。

公开(公告)号：US20080224972A1

公开(公告)日：2008-09-18

申请号：US12081269

申请日：2008-04-14

申请人： Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： G09G3/36 ,  H03M1/66

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/06 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28 ,  G11C27/02 ,  H03K3/35613 ,  H03K19/018521 ,  H03M1/76

摘要： This invention relates to a digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels, a level shift circuit in the shift register has a basic structure of CMOS latch cells and is utilized in each level shift of the clock signal at each transfer stage, a sampling latch circuit with a basic structure of CMOS latch cells has a level shift function, and these respective circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated liquid crystal display device to provide an LCD panel with an extremely narrow picture frame, stable level shift operation, stable sampling & latch operation in a circuit structure having an extremely small number of components, low power consumption and a small surface area.

摘要翻译： 本发明涉及数字/模拟转换器电路，电平移位电路，包含该电平移位电路的移位寄存器，采样锁存电路和锁存电路以及安装有这些各自电路的液晶显示装置，其中驱动器 与包含数字/模拟转换器电路的LCD装置集成的电路具有在基板上以矩阵形式排列的用于像素的开关装置的多晶硅薄膜晶体管，移位寄存器中的电平移位电路具有CMOS锁存单元的基本结构，并且 在每个传输级的时钟信号的每个电平移位中使用的具有CMOS锁存单元的基本结构的采样锁存电路具有电平移位功能，并且这些各个电路可以并入到具有驱动电路的单个扫描型结构电路中 集成液晶显示装置，为LCD面板提供极窄的画面，稳定的电平转换操作 具有极少数量的部件，低功耗和小的表面积的电路结构中的表采样和锁存操作。

公开(公告)号：US20070195038A1

公开(公告)日：2007-08-23

申请号：US11789279

申请日：2007-04-23

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2300/0876 ,  G09G2310/0245 ,  G09G2310/027 ,  G09G2310/06 ,  G09G2310/063 ,  G09G2320/0204 ,  G09G2320/0219 ,  G09G2320/0257 ,  G09G2330/026 ,  G09G2330/027

摘要： A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side. This allows the screen to turn white in a normally white type liquid crystal display, and to turn black in a normally black type liquid crystal display. Image distortion at power on/off time can thus be prevented.

摘要翻译： 一种液晶显示装置，其能够与整个系统相关联地减小尺寸和成本，开始显示在通电时间没有图像失真的图像，并且在断电时关闭屏幕而不进行图像保持;控制方法 液晶显示装置和结合有液晶显示装置的移动终端作为画面显示。 在设置有显示单元（12）的玻璃基板（11）上，诸如接口电路（13），定时发生器（14），参考电压驱动器（15），CS驱动器（18）， 设置VCOM驱动器（19）和电压调节电路（20）以及水平驱动器（16）和垂直驱动器（17）。 当从外部源提供显示复位控制脉冲PCI时，将预定电压写入像素，同时将CS电压和VCOM电压调整到与像素电压相同的电平施加到共电极侧。 这允许屏幕在普通白色液晶显示器中变为白色，并且在常黑型液晶显示器中变黑。 因此可以防止电源开/关时的图像失真。

公开(公告)号：US06664943B1

公开(公告)日：2003-12-16

申请号：US09466969

申请日：1999-12-20

申请人： Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： G09G336

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/06 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28 ,  G11C27/02 ,  H03K3/35613 ,  H03K19/018521 ,  H03M1/76

摘要： This invention relates to a digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels, a level shift circuit in the shift register has a basic structure of CMOS latch cells and is utilized in each level shift of the clock signal at each transfer stage, a sampling latch circuit with a basic structure of CMOS latch cells has a level shift function, and these respective circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated liquid crystal display device to provide an LCD panel with an extremely narrow picture frame, stable level shift operation, stable sampling & latch operation in a circuit structure having an extremely small number of components, low power consumption and a small surface area.

摘要翻译： 本发明涉及数字/模拟转换器电路，电平移位电路，包含该电平移位电路的移位寄存器，采样锁存电路和锁存电路以及安装有这些各自电路的液晶显示装置，其中驱动器 与包含数字/模拟转换器电路的LCD装置集成的电路具有在基板上以矩阵形式排列的用于像素的开关装置的多晶硅薄膜晶体管，移位寄存器中的电平移位电路具有CMOS锁存单元的基本结构，并且 在每个传输级的时钟信号的每个电平移位中使用的具有CMOS锁存单元的基本结构的采样锁存电路具有电平移位功能，并且这些各个电路可以并入到具有驱动电路的单个扫描型结构电路中 集成液晶显示装置，为LCD面板提供极窄的画面，稳定的电平转换操作 具有极少数量的部件，低功耗和小的表面积的电路结构中的表采样和锁存操作。