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1.发明授权Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant 有权通过使用镍前非晶化植入物来增强硅化镍的形成公开(公告)号：US06380057B1
公开(公告)日：2002-04-30
申请号：US09781225
申请日：2001-02-13
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28044 , H01L21/28052 , H01L21/28518
摘要： Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without the formation of rough interfaces between the nickel silicide layers and underlying silicon and without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly in the presence of silicon nitride sidewall spacers.
摘要翻译： 镍自杀化处理通过在沉积Ni之前将镍注入活性区域来实现，以在退火期间催化Ni和Si的反应，以在多晶硅栅极电极和源极/漏极区域上形成NiSi层，而不形成在 硅化镍层和底层硅，并且在栅电极上的金属硅化物层与相关源极/漏极区域上的金属硅化物层之间没有导电桥接，特别是在存在氮化硅侧壁间隔物的情况下。
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2.发明授权Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing 有权使用一步快速热退火工艺和后端加工形成硅化镍的方法公开(公告)号：US06605513B2
公开(公告)日：2003-08-12
申请号：US09729699
申请日：2000-12-06
申请人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
发明人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28061 , H01L21/28518 , H01L29/4933
摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.
摘要翻译： 自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。 在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。 去除未反应的镍。 然后将电介质层沉积在高电阻镍硅化物区域上。 在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。 通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。 将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。
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3.发明授权Dopant implantation processing for improved source/drain interface with metal silicides 有权掺杂剂注入处理，用于改善与金属硅化物的源/漏界面公开(公告)号：US06544872B1
公开(公告)日：2003-04-08
申请号：US09819598
申请日：2001-03-29
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/26513 , H01L21/823418 , H01L21/823814
摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices is avoided, or at least substantially reduced, by increasing the dopant implantation energy to position the maximum source/drain dopant concentration depth below rather than above the depth to which silicidation reaction occurs, thereby minimizing the concentration of dopant in the metal silicide. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.
摘要翻译： 在用于形成MOS晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度通过增加掺杂剂注入能量来定位，以避免或至少大大减少 最大源极/漏极掺杂剂浓度深度低于而不是高于发生硅化反应的深度，从而使金属硅化物中掺杂剂的浓度最小化。 本发明特别适用于在掺杂Si的衬底上形成NiSi层。
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公开(公告)号：US06387767B1
公开(公告)日：2002-05-14
申请号：US09781448
申请日：2001-02-13
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.
摘要翻译： 使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接 和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合 氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。
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公开(公告)号：US06372673B1
公开(公告)日：2002-04-16
申请号：US09781256
申请日：2001-02-13
IPC分类号： H01L21318
CPC分类号： H01L29/665 , H01L21/3185
摘要： Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.
摘要翻译： 通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应， 例如镍。
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6.发明授权Double silicide formation in polysicon gate without silicide in source/drain extensions 有权在源极/漏极延伸部分中没有硅化物的多晶硅栅中形成双重硅化物公开(公告)号：US06451693B1
公开(公告)日：2002-09-17
申请号：US09679370
申请日：2000-10-05
IPC分类号： H01L2144
CPC分类号： H01L29/66613 , H01L21/28518 , H01L29/66507
摘要： A silicide gate contact is formed which is relatively thicker than silicide contacts formed over source/drain regions and shallow junction extensions. A metal layer is first deposited to form silicide over the polysilicon gate and the source/drain extension regions. The silicide is removed from the extension regions, forming shallow junctions, and a layer of silicide remains on the polysilicon gate. A second metal deposition step and silicidation step forms silicide contacts over the source/drain regions and the polysilicon gate. The resulting silicide gate contact is thicker than the resulting silicide contacts over the source/drain regions.
摘要翻译： 形成硅化物栅极接触，其比在源极/漏极区域和浅结延伸部分上形成的硅化物触点相对更厚。 首先沉积金属层以在多晶硅栅极和源极/漏极延伸区域上形成硅化物。 从延伸区域去除硅化物，形成浅结，并且多晶硅栅极上保留一层硅化物。 第二金属沉积步骤和硅化步骤在源极/漏极区域和多晶硅栅极之上形成硅化物接触。 所得到的硅化物栅极接触比源极/漏极区上的所得硅化物接触厚。
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公开(公告)号：US06362095B1
公开(公告)日：2002-03-26
申请号：US09679876
申请日：2000-10-05
IPC分类号： H01L214763
CPC分类号： H01L29/665 , H01L21/28518
摘要： A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.
摘要翻译： 一种制造MOSFET半导体器件的方法包括在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 在栅电极和衬底之间提供栅极氧化物; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 形成设置在源极/漏极区域和栅电极上的硅化镍层，以及两个蚀刻步骤。 在约380-600℃的温度下，在快速热退火期间形成硅化镍层。用硫酸过氧化物混合物进行第一次蚀刻以除去未反应的镍，并且用氨过氧化物混合物进行第二次蚀刻以除去镍 硅化物形成在第一和第二侧壁间隔物上。
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8.发明申请Use of Scanning Theme Implanters and Annealers for Selective Implantation and Annealing 有权使用扫描主题进口机和退火机进行选择性植入和退火公开(公告)号：US20070281450A1
公开(公告)日：2007-12-06
申请号：US11420819
申请日：2006-05-30
IPC分类号： H01L21/04
CPC分类号： H01L21/268 , H01J2237/31701 , H01L21/265
摘要： A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ion implantation is used to first customize circuit areas on the semiconductor wafer by gating ON and OFF the ion beam while semiconductor wafer is scanned. Any inadvertent ion beam interruptions are noted by storing the locations of the interruptions. The wafer is then reprocessed to correct faults caused by the interruptions. The laser anneal tool positions the laser beam over the semiconductor wafer it is then scanned while gating the laser beam ON and OFF to custom anneal the wafer devices. Again, any inadvertent laser beam interruptions are detected and the locations of the interruptions are stored for reprocessing to correct faults.
摘要翻译： 用于集成电路（IC）处理的方法和系统将离子注入工具和激光退火工具组合在具有共享精密X-Y扫描器的单个单元中。 将半导体晶片装载到扫描器的X-Y台上。 定义所需离子注入的数据用于首先通过在扫描半导体晶片时门控ON和OFF离子束来定制半导体晶片上的电路区域。 通过存储中断的位置来注意任何无意的离子束中断。 然后重新处理晶片以纠正由中断引起的故障。 激光退火工具将激光束定位在半导体晶片上，然后扫描激光束，同时选通激光束打开和关闭以定制退火晶片器件。 再次，检测到任何无意的激光束中断，并且存储中断的位置用于重新处理以校正故障。
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9.发明授权Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device 有权用于通过用于非易失性半导体器件的RTA注入退火优化口袋注入轮廓的工艺公开(公告)号：US06410388B1
公开(公告)日：2002-06-25
申请号：US09620480
申请日：2000-07-20
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for fabricating a memory cell in a two-bit EEPROM device, includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with a p-type dopant, wherein the resist mask is used as an ion implant mask, and annealing the semiconductor substrate before implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the annealing of the semiconductor substrate laterally diffuses the p-type dopants to form pocket regions on either side of the EEPROM device.
摘要翻译： 一种用于在2位EEPROM器件中制造存储单元的工艺，包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的抗蚀剂掩模，图案化抗蚀剂掩模，用p型掺杂剂注入半导体衬底， 其中抗蚀剂掩模用作离子注入掩模，并且在用n型掺杂剂注入半导体衬底之前退火半导体衬底。 在一个优选实施例中，半导体衬底的退火横向扩散p型掺杂剂以在EEPROM器件的任一侧上形成袋区。
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公开(公告)号：US06562717B1
公开(公告)日：2003-05-13
申请号：US09679874
申请日：2000-10-05
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/66545
摘要： A method of manufacturing a semiconductor device includes providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; and forming first and second nickel silicide layer respectively disposed on the source/drain regions and the gate electrode. The nickel silicide layer over the gate electrode can be thicker than the nickel silicide layer over the source/drain regions. A semiconductor device formed from the method is also disclosed.
摘要翻译： 一种制造半导体器件的方法包括：在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 以及形成分别设置在源极/漏极区域和栅极电极上的第一和第二硅化镍层。 栅电极上的硅化镍层可以比源/漏区上的硅化镍层厚。 还公开了由该方法形成的半导体器件。
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