公开(公告)号：US06451693B1

公开(公告)日：2002-09-17

申请号：US09679370

申请日：2000-10-05

申请人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

发明人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

IPC分类号： H01L2144

CPC分类号： H01L29/66613 ,  H01L21/28518 ,  H01L29/66507

摘要： A silicide gate contact is formed which is relatively thicker than silicide contacts formed over source/drain regions and shallow junction extensions. A metal layer is first deposited to form silicide over the polysilicon gate and the source/drain extension regions. The silicide is removed from the extension regions, forming shallow junctions, and a layer of silicide remains on the polysilicon gate. A second metal deposition step and silicidation step forms silicide contacts over the source/drain regions and the polysilicon gate. The resulting silicide gate contact is thicker than the resulting silicide contacts over the source/drain regions.

摘要翻译： 形成硅化物栅极接触，其比在源极/漏极区域和浅结延伸部分上形成的硅化物触点相对更厚。 首先沉积金属层以在多晶硅栅极和源极/漏极延伸区域上形成硅化物。 从延伸区域去除硅化物，形成浅结，并且多晶硅栅极上保留一层硅化物。 第二金属沉积步骤和硅化步骤在源极/漏极区域和多晶硅栅极之上形成硅化物接触。 所得到的硅化物栅极接触比源极/漏极区上的所得硅化物接触厚。

公开(公告)号：US06562717B1

公开(公告)日：2003-05-13

申请号：US09679874

申请日：2000-10-05

申请人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

发明人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device includes providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; and forming first and second nickel silicide layer respectively disposed on the source/drain regions and the gate electrode. The nickel silicide layer over the gate electrode can be thicker than the nickel silicide layer over the source/drain regions. A semiconductor device formed from the method is also disclosed.

摘要翻译： 一种制造半导体器件的方法包括：在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 以及形成分别设置在源极/漏极区域和栅极电极上的第一和第二硅化镍层。 栅电极上的硅化镍层可以比源/漏区上的硅化镍层厚。 还公开了由该方法形成的半导体器件。

公开(公告)号：US06387767B1

公开(公告)日：2002-05-14

申请号：US09781448

申请日：2001-02-13

申请人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

发明人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC分类号： H01L21336

CPC分类号： H01L29/665

摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.

摘要翻译： 使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接 和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合 氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。

公开(公告)号：US06362095B1

公开(公告)日：2002-03-26

申请号：US09679876

申请日：2000-10-05

申请人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Jacques Bertrand

发明人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Jacques Bertrand

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.

摘要翻译： 一种制造MOSFET半导体器件的方法包括在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 在栅电极和衬底之间提供栅极氧化物; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 形成设置在源极/漏极区域和栅电极上的硅化镍层，以及两个蚀刻步骤。 在约380-600℃的温度下，在快速热退火期间形成硅化镍层。用硫酸过氧化物混合物进行第一次蚀刻以除去未反应的镍，并且用氨过氧化物混合物进行第二次蚀刻以除去镍 硅化物形成在第一和第二侧壁间隔物上。

公开(公告)号：US06372673B1

公开(公告)日：2002-04-16

申请号：US09781256

申请日：2001-02-13

申请人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

发明人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC分类号： H01L21318

CPC分类号： H01L29/665 ,  H01L21/3185

摘要： Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.

摘要翻译： 通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应， 例如镍。

公开(公告)号：US06724051B1

公开(公告)日：2004-04-20

申请号：US09679877

申请日：2000-10-05

申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  George Jonathan Kluth

发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  George Jonathan Kluth

IPC分类号： H01L2976

CPC分类号： H01L29/665 ,  H01L29/4983 ,  Y10S257/90

摘要： A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first and second sidewall spacers are respectively disposed adjacent the first and second sidewalls. The first and second sidewall spacers are formed from a low-K spacer material that is substantially non-reactive with nickel, for example, SiHC, hydrogen silsesquioxane and methyl silsesquioxane. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： MOSFET半导体器件包括衬底，栅电极，栅极氧化物，第一和第二侧壁间隔物以及镍硅化物层。 栅极氧化物设置在栅极电极和衬底之间，并且衬底包括源极/漏极区域。 栅电极具有第一和第二相对的侧壁，并且第一和第二侧壁间隔件分别设置成与第一和第二侧壁相邻。 第一和第二侧壁间隔物由基本上不与镍反应的低K间隔材料形成，例如SiHC，氢倍半硅氧烷和甲基倍半硅氧烷。 硅化镍层设置在源/漏区和栅电极上。 还公开了制造半导体器件的方法。

公开(公告)号：US06605513B2

公开(公告)日：2003-08-12

申请号：US09729699

申请日：2000-12-06

申请人： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4933

摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

摘要翻译： 自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。 在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。 去除未反应的镍。 然后将电介质层沉积在高电阻镍硅化物区域上。 在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。 通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。 将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

公开(公告)号：US06562718B1

公开(公告)日：2003-05-13

申请号：US09729700

申请日：2000-12-06

申请人： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

发明人： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.

摘要翻译： 形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。 屏蔽层被覆盖在该器件上。 然后露出栅电极的顶表面。 沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏 。

公开(公告)号：US06555453B1

公开(公告)日：2003-04-29

申请号：US10058219

申请日：2002-01-29

申请人： Qi Xiang ,  Christy Mei-Chu Woo ,  George J. Kluth

发明人： Qi Xiang ,  Christy Mei-Chu Woo ,  George J. Kluth

IPC分类号： H01L2128

CPC分类号： H01L29/66507 ,  H01L21/2257 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/4975 ,  H01L29/6659

摘要： Semiconductor devices having fully metal silicided gate electrodes, and methods for making the same, are disclosed. The devices have shallow S/D extensions with depths of less than about 500 Å. The methods for making the subject semiconductor devices employ diffusion of dopant from metal suicides to form shallow S/D extensions, followed by high energy implantation and activation, and metal silicidation to form S/D junctions having metal silicide connect regions and a fully metal silicided electrode.

摘要翻译： 公开了具有完全金属硅化物栅电极的半导体器件及其制造方法。 这些器件具有深度小于约500的浅的S / D延伸。 制造本发明的半导体器件的方法是使用掺杂剂从金属硅化物扩散以形成浅的S / D扩展，接着是高能量注入和激活，以及金属硅化以形成具有金属硅化物连接区域和全金属硅化物的S / D结 电极。

公开(公告)号：US06806172B1

公开(公告)日：2004-10-19

申请号：US09826078

申请日：2001-04-05

申请人： Christy Mei-Chu Woo ,  Eric N. Paton ,  Susan Tover

发明人： Christy Mei-Chu Woo ,  Eric N. Paton ,  Susan Tover

IPC分类号： H01L21425

CPC分类号： H01L29/665 ,  H01L21/324 ,  H01L29/7833

摘要： Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.

摘要翻译： 通过在将镍沉积在基底上或在两个或更多个基底或两者的处理之间加热沉积室来实现镍膜形成。 实施例包括在具有暴露的硅表面的复合材料上形成硅化镍，通过将衬底引入具有至少一个用于加热室的加热元件的PVD室，并将镍层直接沉积在复合材料的暴露的硅表面上，同时加热 具有加热元件的室。