利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

218 条记录 (耗时 0.029 秒)

    Double silicide formation in polysicon gate without silicide in source/drain extensions
    1.
    发明授权
    Double silicide formation in polysicon gate without silicide in source/drain extensions 有权
    在源极/漏极延伸部分中没有硅化物的多晶硅栅中形成双重硅化物

    公开(公告)号：US06451693B1

    公开(公告)日：2002-09-17

    申请号：US09679370

    申请日：2000-10-05

    申请人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

    发明人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

    IPC分类号： H01L2144

    CPC分类号： H01L29/66613 ,  H01L21/28518 ,  H01L29/66507

    摘要： A silicide gate contact is formed which is relatively thicker than silicide contacts formed over source/drain regions and shallow junction extensions. A metal layer is first deposited to form silicide over the polysilicon gate and the source/drain extension regions. The silicide is removed from the extension regions, forming shallow junctions, and a layer of silicide remains on the polysilicon gate. A second metal deposition step and silicidation step forms silicide contacts over the source/drain regions and the polysilicon gate. The resulting silicide gate contact is thicker than the resulting silicide contacts over the source/drain regions.

    摘要翻译： 形成硅化物栅极接触，其比在源极/漏极区域和浅结延伸部分上形成的硅化物触点相对更厚。 首先沉积金属层以在多晶硅栅极和源极/漏极延伸区域上形成硅化物。 从延伸区域去除硅化物，形成浅结，并且多晶硅栅极上保留一层硅化物。 第二金属沉积步骤和硅化步骤在源极/漏极区域和多晶硅栅极之上形成硅化物接触。 所得到的硅化物栅极接触比源极/漏极区上的所得硅化物接触厚。

    Semiconductor device having multiple thickness nickel silicide layers
    2.
    发明授权
    Semiconductor device having multiple thickness nickel silicide layers 有权
    具有多个厚度的硅化镍层的半导体器件

    公开(公告)号：US06562717B1

    公开(公告)日：2003-05-13

    申请号：US09679874

    申请日：2000-10-05

    申请人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

    发明人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

    IPC分类号： H01L2144

    CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/66545

    摘要： A method of manufacturing a semiconductor device includes providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; and forming first and second nickel silicide layer respectively disposed on the source/drain regions and the gate electrode. The nickel silicide layer over the gate electrode can be thicker than the nickel silicide layer over the source/drain regions. A semiconductor device formed from the method is also disclosed.

    摘要翻译： 一种制造半导体器件的方法包括：在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 以及形成分别设置在源极/漏极区域和栅极电极上的第一和第二硅化镍层。 栅电极上的硅化镍层可以比源/漏区上的硅化镍层厚。 还公开了由该方法形成的半导体器件。

    Fully nickel silicided metal gate with shallow junction formed
    3.
    发明授权
    Fully nickel silicided metal gate with shallow junction formed 有权
    全镍硅化金属栅极，形成浅结

    公开(公告)号：US06555453B1

    公开(公告)日：2003-04-29

    申请号：US10058219

    申请日：2002-01-29

    申请人： Qi Xiang ,  Christy Mei-Chu Woo ,  George J. Kluth

    发明人： Qi Xiang ,  Christy Mei-Chu Woo ,  George J. Kluth

    IPC分类号： H01L2128

    CPC分类号： H01L29/66507 ,  H01L21/2257 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/4975 ,  H01L29/6659

    摘要： Semiconductor devices having fully metal silicided gate electrodes, and methods for making the same, are disclosed. The devices have shallow S/D extensions with depths of less than about 500 Å. The methods for making the subject semiconductor devices employ diffusion of dopant from metal suicides to form shallow S/D extensions, followed by high energy implantation and activation, and metal silicidation to form S/D junctions having metal silicide connect regions and a fully metal silicided electrode.

    摘要翻译： 公开了具有完全金属硅化物栅电极的半导体器件及其制造方法。 这些器件具有深度小于约500的浅的S / D延伸。 制造本发明的半导体器件的方法是使用掺杂剂从金属硅化物扩散以形成浅的S / D扩展，接着是高能量注入和激活，以及金属硅化以形成具有金属硅化物连接区域和全金属硅化物的S / D结 电极。

    Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts
    5.
    发明授权
    Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts 有权
    制造具有过饱和源极/漏极延伸部分和金属硅化物触点的半导体器件的方法

    公开(公告)号：US06797602B1

    公开(公告)日：2004-09-28

    申请号：US10071207

    申请日：2002-02-11

    申请人： George Jonathan Kluth ,  Qi Xiang

    发明人： George Jonathan Kluth ,  Qi Xiang

    IPC分类号： H01L213205

    CPC分类号： H01L29/6653 ,  H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7834

    摘要： Semiconductor devices, such as transistors, with a supersaturated concentration of dopant in the source/drain extension and metal silicide contacts enable the production of smaller, higher speed devices. Supersaturated source/drain extensions are subject to dopant diffusion out from the source/drain extension during high temperature metal silicide contact formation. The formation of lower temperature metal silicide contacts, such as nickel silicide contacts, prevents dopant diffusion and maintains the source/drain extensions in a supersaturated state throughout semiconductor device manufacturing.

    摘要翻译： 在源极/漏极延伸和金属硅化物触点中具有过饱和浓度的掺杂剂的晶体管等半导体器件能够生产更小更高速度的器件。 在高温金属硅化物接触形成期间，过饱和源极/漏极延伸部分从源极/漏极延伸部分扩散出来。 低温金属硅化物接触（例如硅化镍接触）的形成防止掺杂剂扩散，并且在整个半导体器件制造过程中将源极/漏极延伸部保持在过饱和状态。

    Dopant implantation processing for improved source/drain interface with metal silicides
    6.
    发明授权
    Dopant implantation processing for improved source/drain interface with metal silicides 有权
    掺杂剂注入处理，用于改善与金属硅化物的源/漏界面

    公开(公告)号：US06544872B1

    公开(公告)日：2003-04-08

    申请号：US09819598

    申请日：2001-03-29

    申请人： Matthew S. Buynoski ,  Qi Xiang ,  George Jonathan Kluth

    发明人： Matthew S. Buynoski ,  Qi Xiang ,  George Jonathan Kluth

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823814

    摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices is avoided, or at least substantially reduced, by increasing the dopant implantation energy to position the maximum source/drain dopant concentration depth below rather than above the depth to which silicidation reaction occurs, thereby minimizing the concentration of dopant in the metal silicide. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.

    摘要翻译： 在用于形成MOS晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度通过增加掺杂剂注入能量来定位，以避免或至少大大减少 最大源极/漏极掺杂剂浓度深度低于而不是高于发生硅化反应的深度，从而使金属硅化物中掺杂剂的浓度最小化。 本发明特别适用于在掺杂Si的衬底上形成NiSi层。

    Integrated circuits with asymmetric and stacked transistors
    8.
    发明授权
    Integrated circuits with asymmetric and stacked transistors 有权
    具有不对称和堆叠晶体管的集成电路

    公开(公告)号：US08482963B1

    公开(公告)日：2013-07-09

    申请号：US12629831

    申请日：2009-12-02

    申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

    摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

    Field effect transistor having increased carrier mobility
    9.
    发明授权
    Field effect transistor having increased carrier mobility 有权
    场效应晶体管的载流子迁移率增加

    公开(公告)号：US07923785B2

    公开(公告)日：2011-04-12

    申请号：US10643461

    申请日：2003-08-18

    申请人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    发明人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

    摘要： According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

    摘要翻译： 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。