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11 条记录 (耗时 0.026 秒)

    METHODOLOGY FOR EVALUATION OF ELECTRICAL CHARACTERISTICS OF CARBON NANOTUBES
    4.
    发明申请
    METHODOLOGY FOR EVALUATION OF ELECTRICAL CHARACTERISTICS OF CARBON NANOTUBES 有权
    碳纳米管电气特性评价方法

    公开(公告)号：US20120301980A1

    公开(公告)日：2012-11-29

    申请号：US13569394

    申请日：2012-08-08

    申请人： Maxime Darnon ,  Gerald W. Gibson ,  Pratik P. Joshi ,  Qinghuang Lin

    发明人： Maxime Darnon ,  Gerald W. Gibson ,  Pratik P. Joshi ,  Qinghuang Lin

    IPC分类号： H01L21/66

    CPC分类号： H01L23/53276 ,  B82Y35/00 ,  B82Y40/00 ,  H01L21/76808 ,  H01L21/76835 ,  H01L21/76885 ,  H01L22/14 ,  H01L2221/1031 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： The present disclosure relates to a structure comprising 1. an electrically conductive substrate having carbon nanotubes grown thereon; 2. a cured polymeric fill matrix comprising at least one latent photoacid generator embedded around the carbon nanotubes but allowing tips of the carbon nantotubes to be exposed; 3. a layer of patterned and cured photosensitive dielectric material on the cured polymeric fill matrix, wherein tips of the carbon nantobues are exposed within the patterns; and 4. an electrically conductive material filled into the interconnect pattern and in contact with the exposed tips of the carbon nanotubes; and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.

    摘要翻译： 本公开涉及一种结构，其包括：其上生长有碳纳米管的导电基材; 2.一种固化的聚合物填充基质，其包含嵌入碳纳米管周围的至少一个潜在光致酸发生剂，但允许碳纳米管的尖端暴露; 在固化的聚合物填充基质上的一层图案化和固化的光敏电介质材料，其中碳纳米管的尖端在图案内暴露; 4.一种填充到互连图案中并与碳纳米管的暴露尖端接触的导电材料; 以及制造该结构并使用该结构来测量碳纳米管的电特性的方法。

    Damascene structure having a metal-oxide-metal capacitor associated therewith
    7.
    发明授权
    Damascene structure having a metal-oxide-metal capacitor associated therewith 有权
    具有与其相关联的金属氧化物 - 金属电容器的镶嵌结构

    公开(公告)号：US06680542B1

    公开(公告)日：2004-01-20

    申请号：US09575214

    申请日：2000-05-18

    申请人： Gerald W. Gibson ,  Richard W. Gregor ,  Chun-Yung Sung ,  Daniel J. Vitkavage ,  Allen Yen

    发明人： Gerald W. Gibson ,  Richard W. Gregor ,  Chun-Yung Sung ,  Daniel J. Vitkavage ,  Allen Yen

    IPC分类号： H01L2348

    CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.

    摘要翻译： 本发明提供一种包括互连和电容器的半导体器件及其制造方法。 该方法包括通过层间电介质层和位于层间电介质下面的电介质蚀刻停止层形成镶嵌互连结构，其中镶嵌互连结构接触第一互连结构。 该方法还包括通过层间电介质层形成金属氧化物金属（MOM）电容器镶嵌结构，并终止在介电蚀刻停止层上。 在替代实施例中，镶嵌结构可以是双镶嵌结构。 此外，在另一个实施例中，镶嵌互连结构和MOM电容器可以构成较大集成电路的一部分。

    METHOD OF WAFER THINNING
    8.
    发明申请
    METHOD OF WAFER THINNING 审中-公开
    减薄方法

    公开(公告)号：US20080173972A1

    公开(公告)日：2008-07-24

    申请号：US11624824

    申请日：2007-01-19

    申请人： Gerald W. Gibson

    发明人： Gerald W. Gibson

    IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L21/302

    CPC分类号： H01L22/26 ,  H01L21/3065

    摘要： A method for thinning a semiconductor wafer, the method includes selecting a semiconductor wafer having a buried stop layer; and planarizing the semiconductor wafer to the buried stop layer to produce a thin semiconductor wafer.

    摘要翻译： 一种用于稀薄半导体晶片的方法，所述方法包括选择具有掩埋停止层的半导体晶片; 并且将半导体晶片平面化到掩埋停止层以产生薄的半导体晶片。

    SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING
    9.
    发明申请
    SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING 审中-公开
    选择性外来成长通过孵化时间工程

    公开(公告)号：US20120295417A1

    公开(公告)日：2012-11-22

    申请号：US13109567

    申请日：2011-05-17

    申请人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

    发明人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66628 ,  H01L21/0237 ,  H01L21/02524 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/78

    摘要： A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.

    摘要翻译： 提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。 通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率 ，或通过改变掩模层的表面以获得适当的成核特性。 或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。

    Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer
    10.
    发明授权
    Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer 失效
    低k或超低k层间电介质图案转移的结构和方法

    公开(公告)号：US07695897B2

    公开(公告)日：2010-04-13

    申请号：US11429709

    申请日：2006-05-08

    申请人： James J. Bucchignano ,  Gerald W. Gibson ,  Mary B. Rothwell ,  Roy R. Yu

    发明人： James J. Bucchignano ,  Gerald W. Gibson ,  Mary B. Rothwell ,  Roy R. Yu

    IPC分类号： G03F7/00 ,  G03F7/26

    CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76813

    摘要： The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.

    摘要翻译： 本发明涉及用于形成低k或超低k（即介电常数范围为约1.5至约3.5）层间电介质（ILD）材料的互连图案的改进方法和结构。 具体地说，减小的光刻关键尺寸（CD）（即与目标CD相比）最初用于形成具有增加的厚度的图案化抗蚀剂层，其又允许使用包括下部氮化物掩模层的简单硬掩模层， 用于随后的图案转印的上氧化物掩模层。 接下来通过使用含氧化学物质的第一反应离子蚀刻（RIE）工艺来形成硬掩模叠层，以形成具有与目标CD基本相同的恢复的CD的硬掩模开口。 然后通过使用含氮化学物质的第二RIE方法将ILD材料图案化，以形成与目标CD的互连图案。