公开(公告)号：US20150154336A1

公开(公告)日：2015-06-04

申请号：US14535328

申请日：2014-11-07

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Shen-Yu Huang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40 ,  G06F2217/78 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0612 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract translation: 本发明提供了一种倒装芯片封装协同设计方法。 该方法包括以下步骤：提供芯片的I / O焊盘信息和PCB的连接信息; 根据芯片的I / O焊盘信息和PCB的连接信息执行第一I / O焊盘放置; 利用RDL路由分析装置对芯片的第一I / O焊盘放置执行凸块焊盘间距分析以产生凸块焊盘间距分析结果; 根据凸点焊盘间距分析结果对封装进行凸块焊接规划，以产生焊盘规划结果; 以及根据所述凸块焊盘规划结果对所述芯片执行第二I / O焊盘放置以产生I / O焊盘放置结果。

公开(公告)号：US09552452B2

公开(公告)日：2017-01-24

申请号：US15088109

申请日：2016-03-31

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Shen-Yu Huang

IPC: G06F17/50 ,  H01L23/00

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40 ,  G06F2217/78 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0612 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract translation: 本发明提供了一种倒装芯片封装协同设计方法。 该方法包括以下步骤：提供芯片的I / O焊盘信息和PCB的连接信息; 根据芯片的I / O焊盘信息和PCB的连接信息执行第一I / O焊盘放置; 利用RDL路由分析装置对芯片的第一I / O焊盘放置执行凸块焊盘间距分析以产生凸块焊盘间距分析结果; 根据凸点焊盘间距分析结果对封装进行凸块焊接规划，以产生焊盘规划结果; 以及根据所述凸块焊盘规划结果对所述芯片执行第二I / O焊盘放置以产生I / O焊盘放置结果。

公开(公告)号：US09379079B1

公开(公告)日：2016-06-28

申请号：US14636137

申请日：2015-03-02

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Shen-Yu Huang

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/488

CPC classification number: H01L23/5283 ,  H01L24/14 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179

Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.

Abstract translation: 本发明提供一种倒装芯片方案和一种形成倒装芯片方案。 倒装芯片方案包括：多个凸块，分别以第一图案布置的一些凸块，并且分别以与第一图案不同的第二图案布置的一些凸块; 其中所述第一图案是由三个凸起布置的等边三角形，并且所述第二图案是由四个凸块布置的正方形。 该方法包括：分别以一第一图案布置一些凸块，并分别以与第一图案不同的第二图案布置一些凸块; 其中所述第一图案是由三个凸起布置的等边三角形，并且所述第二图案是由四个凸块布置的正方形。

公开(公告)号：US09589092B2

公开(公告)日：2017-03-07

申请号：US14546238

申请日：2014-11-18

Applicant: MediaTek Inc.

Inventor： Jia-Wei Fang ,  Chi-Jih Shih ,  Shen-Yu Huang

IPC: G06F17/50 ,  H01L23/00

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40 ,  G06F2217/78 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0612 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.

Abstract translation: 提供了一种用于共同设计倒装芯片和插入器的方法。 获得关于倒装芯片的I / O焊盘，电源引脚和IR约束的信息。 根据该信息进行碰撞计划程序以获得倒装芯片的微小凸块的总数，并且根据凸块的凸起位置获得倒装芯片的每个电源引脚的最小电导 倒装芯片。 执行芯片插入器路由过程以根据倒装芯片的电源引脚的最小电导获得倒装芯片的重分布层（RDL）路由和插入器的插入器布线。

公开(公告)号：US20160217244A1

公开(公告)日：2016-07-28

申请号：US15088109

申请日：2016-03-31

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Shen-Yu Huang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40 ,  G06F2217/78 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0612 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract translation: 本发明提供了一种倒装芯片封装协同设计方法。 该方法包括以下步骤：提供芯片的I / O焊盘信息和PCB的连接信息; 根据芯片的I / O焊盘信息和PCB的连接信息执行第一I / O焊盘放置; 利用RDL路由分析装置对芯片的第一I / O焊盘放置执行凸块焊盘间距分析以产生凸块焊盘间距分析结果; 根据凸点焊盘间距分析结果对封装进行凸块焊接规划，以产生焊盘规划结果; 以及根据所述凸块焊盘规划结果对所述芯片执行第二I / O焊盘放置以产生I / O焊盘放置结果。

公开(公告)号：US20160190083A1

公开(公告)日：2016-06-30

申请号：US14636137

申请日：2015-03-02

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Shen-Yu Huang

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L24/14 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179

Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.

Abstract translation: 本发明提供一种倒装芯片方案和一种形成倒装芯片方案。 倒装芯片方案包括：多个凸块，分别以第一图案布置的一些凸块，并且分别以与第一图案不同的第二图案布置的一些凸块; 其中所述第一图案是由三个凸起布置的等边三角形，并且所述第二图案是由四个凸块布置的正方形。 该方法包括：分别以一第一图案布置一些凸块，并分别以与第一图案不同的第二图案布置一些凸块; 其中所述第一图案是由三个凸起布置的等边三角形，并且所述第二图案是由四个凸块布置的正方形。

公开(公告)号：US09305131B2

公开(公告)日：2016-04-05

申请号：US14535328

申请日：2014-11-07

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Shen-Yu Huang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40 ,  G06F2217/78 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0612 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract translation: 本发明提供了一种倒装芯片封装协同设计方法。 该方法包括以下步骤：提供芯片的I / O焊盘信息和PCB的连接信息; 根据芯片的I / O焊盘信息和PCB的连接信息执行第一I / O焊盘放置; 利用RDL路由分析装置对芯片的第一I / O焊盘放置执行凸块焊盘间距分析以产生凸块焊盘间距分析结果; 根据凸点焊盘间距分析结果对封装进行凸块焊接规划，以产生焊盘规划结果; 以及根据所述凸块焊盘规划结果对所述芯片执行第二I / O焊盘放置以产生I / O焊盘放置结果。