公开(公告)号：US09904751B2

公开(公告)日：2018-02-27

申请号：US14743066

申请日：2015-06-18

Applicant: MediaTek Inc.

Inventor： Jia-Wei Fang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40

Abstract: The invention provides a method of designing an integrated circuit. The method includes providing a physical layout group including a first layout corresponding to a first die having a first function. A second layout corresponds to an interposer configured for the first die connected thereon. The first physical layout group is partitioned into a first physical layout partition according to the first function. A first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. A first verification is performed on the first hierarchical layout.

公开(公告)号：US20150154336A1

公开(公告)日：2015-06-04

申请号：US14535328

申请日：2014-11-07

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Shen-Yu Huang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40 ,  G06F2217/78 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0612 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract translation: 本发明提供了一种倒装芯片封装协同设计方法。 该方法包括以下步骤：提供芯片的I / O焊盘信息和PCB的连接信息; 根据芯片的I / O焊盘信息和PCB的连接信息执行第一I / O焊盘放置; 利用RDL路由分析装置对芯片的第一I / O焊盘放置执行凸块焊盘间距分析以产生凸块焊盘间距分析结果; 根据凸点焊盘间距分析结果对封装进行凸块焊接规划，以产生焊盘规划结果; 以及根据所述凸块焊盘规划结果对所述芯片执行第二I / O焊盘放置以产生I / O焊盘放置结果。

公开(公告)号：US10067000B2

公开(公告)日：2018-09-04

申请号：US14855592

申请日：2015-09-16

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang ,  Yi-Feng Chen ,  Jia-Wei Fang

IPC: G01K7/01 ,  G01K7/00 ,  H03K3/03

Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

公开(公告)号：US09904752B2

公开(公告)日：2018-02-27

申请号：US14986275

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Zwei-Mei Lee ,  Bo-Jr Huang ,  Chi-Jih Shih ,  Jia-Wei Fang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5009 ,  G06F17/505 ,  G06F2217/78

Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

公开(公告)号：US09490808B2

公开(公告)日：2016-11-08

申请号：US14926775

申请日：2015-10-29

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang ,  Jia-Wei Fang

IPC: H03K17/296 ,  H03K19/003 ,  H03K5/14 ,  G06F1/24 ,  H03K17/22 ,  H03K19/20

CPC classification number: H03K19/00361 ,  G06F1/24 ,  H03K5/14 ,  H03K17/223 ,  H03K19/20

Abstract: A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one feedback switch. The delay unit generates a delay signal according to an input signal and a reset signal. The cascading switch selectively passes the delay signal according to a control signal. The feedback switch selectively forms a feedback path of the delay unit according to the control signal. The decoder generates an output signal according to the delay signal. The delay unit is supplied by a work voltage. If the work voltage has noise, the noise will be detectable by analyzing the output signal of the decoder.

Abstract translation: 感测电路包括延迟链和解码器。 延迟链包括至少一个延迟单元，至少一个级联开关和至少一个反馈开关。 延迟单元根据输入信号和复位信号生成延迟信号。 级联开关根据控制信号选择性地传递延迟信号。 反馈开关根据控制信号选择性地形成延迟单元的反馈路径。 解码器根据延迟信号产生输出信号。 延迟单元由工作电压提供。 如果工作电压具有噪声，则可以通过分析解码器的输出信号来检测噪声。

公开(公告)号：US20160211318A1

公开(公告)日：2016-07-21

申请号：US14925995

申请日：2015-10-29

Applicant: MEDIATEK INC.

Inventor： Chao-Yang Yeh ,  Chee-Kong Ung ,  Tzu-Hung Lin ,  Jia-Wei Fang

IPC: H01L49/02 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L28/40 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/16 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/014

Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.

Abstract translation: 微电子封装包括具有芯片安装表面的封装衬底; 芯片安装在封装基板的芯片安装表面上，芯片的有源表面朝向芯片安装表面; 分布在芯片的有源表面上的多个输入/输出（I / O）焊盘; 以及安装在芯片的有源表面上的分立无源元件。 分立无源元件可以是去耦电容器，电阻器或电感器。

公开(公告)号：US11989005B2

公开(公告)日：2024-05-21

申请号：US17490663

申请日：2021-09-30

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang ,  Jia-Wei Fang ,  Jia-Ming Chen ,  Ya-Ting Chang ,  Chien-Yuan Lai ,  Cheng-Yuh Wu ,  Yi-Pin Lin ,  Wen-Wen Hsieh ,  Min-Shu Wang

IPC: G06F1/20 ,  G05B19/4155

CPC classification number: G05B19/4155 ,  G06F1/206 ,  G05B2219/50333

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

公开(公告)号：US20170243814A1

公开(公告)日：2017-08-24

申请号：US15590021

申请日：2017-05-09

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Tzu-Hung Lin

IPC: H01L23/498 ,  H01L23/482

CPC classification number: H01L23/49811 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/06 ,  H01L24/09 ,  H01L25/065 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/08235 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579

Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.

公开(公告)号：US09679830B2

公开(公告)日：2017-06-13

申请号：US14830727

申请日：2015-08-19

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Tzu-Hung Lin

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/532 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/49811 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/06 ,  H01L24/09 ,  H01L25/065 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/08235 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579

Abstract: A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die assembled on the first surface of the packaging substrate. The semiconductor die includes a plurality of first bump pads and second bump pads on an active surface of the semiconductor die, a plurality of first copper pillars on the first bump pads, and a plurality of second copper pillars on the second bump pads. The first copper pillars have a diameter that is smaller than that of the second copper pillars.

公开(公告)号：US09589092B2

公开(公告)日：2017-03-07

申请号：US14546238

申请日：2014-11-18

Applicant: MediaTek Inc.

Inventor： Jia-Wei Fang ,  Chi-Jih Shih ,  Shen-Yu Huang

IPC: G06F17/50 ,  H01L23/00

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40 ,  G06F2217/78 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0612 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.

Abstract translation: 提供了一种用于共同设计倒装芯片和插入器的方法。 获得关于倒装芯片的I / O焊盘，电源引脚和IR约束的信息。 根据该信息进行碰撞计划程序以获得倒装芯片的微小凸块的总数，并且根据凸块的凸起位置获得倒装芯片的每个电源引脚的最小电导 倒装芯片。 执行芯片插入器路由过程以根据倒装芯片的电源引脚的最小电导获得倒装芯片的重分布层（RDL）路由和插入器的插入器布线。