公开(公告)号：US20240096861A1

公开(公告)日：2024-03-21

申请号：US18454220

申请日：2023-08-23

Applicant: MEDIATEK INC.

Inventor： Che-Hung KUO ,  Hsiao-Yun CHEN ,  Wen-Pin CHU ,  Chun-Hsiang HUANG

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5385 ,  H01L28/90 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.

公开(公告)号：US20160307873A1

公开(公告)日：2016-10-20

申请号：US15006386

申请日：2016-01-26

Applicant: MediaTek Inc.

Inventor： Ying-Chih CHEN ,  Che-Ya CHOU ,  Min-Yu LIN ,  Chia-Hao YANG ,  Wen-Pin CHU

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3171 ,  H01L23/4821 ,  H01L23/544 ,  H01L24/06 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2223/5446 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/4813 ,  H01L2224/49052 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: A semiconductor memory package is provided. The package includes a semiconductor die having a first die portion and a second die portion. A post-passivation layer is on the semiconductor die. A first post-passivation interconnect (PPI) structure includes pluralities of first and second pads arranged in first and second tiers, respectively. The first and second pads are disposed on a first die portion of the semiconductor die. A second PPI structure includes pluralities of third and fourth pads arranged in third and fourth tiers, respectively. The third and fourth pads are disposed on a second die portion of the semiconductor die. One of the first pads and one of the fourth pads are coupled to each other by a first bonding wire. One of the second pads and one of the third pads are coupled to each other.

Abstract translation: 提供半导体存储器封装。 该封装包括具有第一管芯部分和第二管芯部分的半导体管芯。 后半导体裸片上的钝化层。 第一后钝化互连（PPI）结构包括分别布置在第一和第二层中的多个第一和第二焊盘。 第一和第二焊盘设置在半导体管芯的第一管芯部分上。 第二PPI结构分别包括排列在第三和第四层中的多个第三和第四垫。 第三和第四焊盘设置在半导体管芯的第二管芯部分上。 第一焊盘之一和第四焊盘之一通过第一接合线彼此耦合。 第二焊盘中的一个和第三焊盘中的一个彼此耦合。