公开(公告)号：US20170103967A1

公开(公告)日：2017-04-13

申请号：US15385988

申请日：2016-12-21

Applicant: MediaTek Inc.

Inventor： Hsing-Chih LIU ,  Chia-Hao YANG ,  Ying-Chih CHEN

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/4903 ,  H01L2224/4909 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/4554

Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.

公开(公告)号：US20150333039A1

公开(公告)日：2015-11-19

申请号：US14809482

申请日：2015-07-27

Applicant: MediaTek Inc.

Inventor： Hsing-Chih LIU ,  Chia-Hao YANG ,  Ying-Chih CHEN

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/4903 ,  H01L2224/4909 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/4554

Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.

Abstract translation: 半导体封装结构包括基底。 第一个模具安装在基座上。 第一管芯包括多个第一焊盘，第一焊盘区域布置在第一层中。 具有第二焊盘区域的多个第二焊盘被布置在第二层中。 第二个模具安装在基座上。 第二管芯包括布置在第三层中的多个第三焊盘。 第一接合线具有分别耦合到第一焊盘之一和第三焊盘中的一个的两个端子。 第二接合线具有分别耦合到第三焊盘之一和第二焊盘之一的两个端子。

公开(公告)号：US20160307873A1

公开(公告)日：2016-10-20

申请号：US15006386

申请日：2016-01-26

Applicant: MediaTek Inc.

Inventor： Ying-Chih CHEN ,  Che-Ya CHOU ,  Min-Yu LIN ,  Chia-Hao YANG ,  Wen-Pin CHU

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3171 ,  H01L23/4821 ,  H01L23/544 ,  H01L24/06 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2223/5446 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/4813 ,  H01L2224/49052 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: A semiconductor memory package is provided. The package includes a semiconductor die having a first die portion and a second die portion. A post-passivation layer is on the semiconductor die. A first post-passivation interconnect (PPI) structure includes pluralities of first and second pads arranged in first and second tiers, respectively. The first and second pads are disposed on a first die portion of the semiconductor die. A second PPI structure includes pluralities of third and fourth pads arranged in third and fourth tiers, respectively. The third and fourth pads are disposed on a second die portion of the semiconductor die. One of the first pads and one of the fourth pads are coupled to each other by a first bonding wire. One of the second pads and one of the third pads are coupled to each other.

Abstract translation: 提供半导体存储器封装。 该封装包括具有第一管芯部分和第二管芯部分的半导体管芯。 后半导体裸片上的钝化层。 第一后钝化互连（PPI）结构包括分别布置在第一和第二层中的多个第一和第二焊盘。 第一和第二焊盘设置在半导体管芯的第一管芯部分上。 第二PPI结构分别包括排列在第三和第四层中的多个第三和第四垫。 第三和第四焊盘设置在半导体管芯的第二管芯部分上。 第一焊盘之一和第四焊盘之一通过第一接合线彼此耦合。 第二焊盘中的一个和第三焊盘中的一个彼此耦合。

公开(公告)号：US20160268233A1

公开(公告)日：2016-09-15

申请号：US15012018

申请日：2016-02-01

Applicant: MediaTek Inc.

Inventor： Che-Hung KUO ,  Ying-Chih CHEN ,  Che-Ya CHOU

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48265 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一衬底。 第一半导体管芯设置在第一衬底上。 无源器件直接位于第一半导体管芯上。 无源器件在平面图中设置在第一半导体管芯的边界内。

公开(公告)号：US20180033774A1

公开(公告)日：2018-02-01

申请号：US15726471

申请日：2017-10-06

Applicant: MediaTek Inc

Inventor： Che-Hung KUO ,  Ying-Chih CHEN ,  Che-Ya CHOU

IPC: H01L25/065 ,  H01L25/16

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48265 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.