公开(公告)号：US20130109157A1

公开(公告)日：2013-05-02

申请号：US13723601

申请日：2012-12-21

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US20120135593A1

公开(公告)日：2012-05-31

申请号：US13366509

申请日：2012-02-06

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US20100224928A1

公开(公告)日：2010-09-09

申请号：US12714905

申请日：2010-03-01

申请人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa

发明人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L27/11578 ,  H01L21/28282 ,  H01L27/11582

摘要： A method for manufacturing a nonvolatile semiconductor memory device, the device including a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction and a semiconductor pillar piercing the stacked structural unit in the first direction, the method includes: forming a stacked unit including a core material film alternately stacked with a sacrificial film on a major surface of a substrate perpendicular to the first direction; making a trench in the stacked unit, the trench extending in the first direction and a second direction in a plane perpendicular to the first direction; filling a filling material into the trench; removing the sacrificial film to form a hollow structural unit, the hollow structural unit including a post unit supporting the core material film on the substrate, the post unit being made of the filling material; and forming the stacked structural unit by stacking one of the insulating films and one of the electrode films on a surface of the core material film exposed by removing the sacrificial film.

摘要翻译： 一种用于制造非易失性半导体存储器件的方法，该器件包括层叠结构单元，该堆叠结构单元包括在第一方向上交替堆叠多个电极膜的多个绝缘膜，以及沿第一方向穿透层叠结构单元的半导体柱， 方法包括：在垂直于第一方向的基板的主表面上形成包括交替堆叠有牺牲膜的芯材膜的堆叠单元; 在所述堆叠单元中形成沟槽，所述沟槽在垂直于所述第一方向的平面中沿所述第一方向延伸并且沿第二方向延伸; 将填充材料填充到沟槽中; 去除所述牺牲膜以形成中空结构单元，所述中空结构单元包括支撑所述芯材膜的柱单元，所述柱单元由所述填充材料制成; 以及通过将绝缘膜和其中一个电极膜层叠在通过去除牺牲膜而暴露的芯材膜的表面上来形成层叠结构单元。

公开(公告)号：US20100072538A1

公开(公告)日：2010-03-25

申请号：US12534576

申请日：2009-08-03

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US20100320526A1

公开(公告)日：2010-12-23

申请号：US12727730

申请日：2010-03-19

申请人： Masaru KIDOH ,  Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Yoshimasa MIKAJIRI ,  Shigeto OOTA ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI

发明人： Masaru KIDOH ,  Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Yoshimasa MIKAJIRI ,  Shigeto OOTA ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L23/522 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a memory unit; and a circuit unit provided between the semiconductor substrate and the memory unit. The memory unit includes: a stacked structural unit having electrode films alternately stacked with inter-electrode-film insulating films; a semiconductor pillar piercing the stacked structural unit; and a storage unit provided corresponding to an intersection between the electrode films and the semiconductor pillar. The circuit unit includes first and second transistors having different conductivity type, a first interconnect, and first and second contact plugs. The first interconnect includes silicide provided on a side of the first and second transistors opposite to the semiconductor substrate. The first contact plug made of polysilicon of the first conductivity type connects the first interconnect to the first transistor. The second contact plug made of polysilicon of the second conductivity type connects the first interconnect to the second transistor.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 记忆单元 以及设置在半导体衬底和存储器单元之间的电路单元。 存储单元包括：层叠结构单元，其具有交替层叠有电极间绝缘膜的电极膜; 穿过堆叠结构单元的半导体柱; 以及与电极膜和半导体柱之间的交点对应地设置的存储单元。 电路单元包括具有不同导电类型的第一和第二晶体管，第一互连以及第一和第二接触插塞。 第一互连包括设置在与半导体衬底相对的第一和第二晶体管一侧的硅化物。 由第一导电类型的多晶硅制成的第一接触插头将第一互连件连接到第一晶体管。 由第二导电类型的多晶硅制成的第二接触插头将第一互连件连接到第二晶体管。

公开(公告)号：US20100171162A1

公开(公告)日：2010-07-08

申请号：US12647836

申请日：2009-12-28

申请人： Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KITO ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Masaru KIDOH ,  Yoshiaki FUKUZUMI

发明人： Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KITO ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Masaru KIDOH ,  Yoshiaki FUKUZUMI

IPC分类号： H01L27/088 ,  H01L21/822

CPC分类号： H01L27/11578 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer formed to surround a side surface of the first semiconductor layer; and a first conductive layer formed to surround a side surface of the electric charge accumulation layer. The columnar portions are aligned at a first pitch in a first direction orthogonal to the vertical direction, and arranged in a staggered pattern at a second pitch in a second direction orthogonal to the vertical and first directions. The first conductive layers are configured to be arranged at the first pitch in the first direction, and extend to curve in a wave-like fashion in the second direction along the staggered-pattern arrangement.

摘要翻译： 每个存储串包括：第一半导体层，具有在垂直方向上延伸到基板的一对柱状部分和形成为连接该一对柱状部分的下端的接合部分; 形成为包围第一半导体层的侧面的电荷蓄积层; 以及形成为围绕电荷蓄积层的侧表面的第一导电层。 柱状部分在垂直于垂直方向的第一方向上以第一间距排列，并且在垂直于垂直方向和第一方向的第二方向上以第二间距布置成交错图案。 第一导电层被配置为沿着第一方向以第一间距布置，并且沿着交错图案布置在第二方向上以波浪形的方式延伸。

公开(公告)号：US20100117137A1

公开(公告)日：2010-05-13

申请号：US12559865

申请日：2009-09-15

申请人： Yoshiaki FUKUZUMI ,  Masaru KITO ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

发明人： Yoshiaki FUKUZUMI ,  Masaru KITO ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.

摘要翻译： 每个存储器串都具有第一半导体层，该第一半导体层具有相对于衬底沿垂直方向延伸的一对柱状部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕电荷存储层的第一导电层。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 形成为围绕所述第二半导体层的侧表面的栅极绝缘层; 以及形成为围绕所述栅极绝缘层的第二导电层。 第二半导体层的有效杂质浓度小于或等于第一半导体层的有效杂质浓度。

公开(公告)号：US20120064683A1

公开(公告)日：2012-03-15

申请号：US13301442

申请日：2011-11-21

申请人： Megumi ISHIDUKI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Hideaki AOCHI

发明人： Megumi ISHIDUKI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Hideaki AOCHI

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.

摘要翻译： 通过在与硅衬底的上表面正交的方向上交替堆叠用作控制栅极和电介质膜的电极膜来形成多层体。 在多层体中形成在字线方向上延伸的沟槽，并且在沟槽的内表面上形成记忆膜。 随后，将硅体埋在沟槽内，并且电荷存储膜和硅体在字线方向上分开以形成硅柱。 这简化了位线方向上的存储单元的配置，因此可以缩短硅柱的排列间距，减小每个存储单元的面积。

公开(公告)号：US20100207194A1

公开(公告)日：2010-08-19

申请号：US12706127

申请日：2010-02-16

申请人： Hiroyasu TANAKA ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Junya MATSUNAMI ,  Ryouhei KIRISAWA

发明人： Hiroyasu TANAKA ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Junya MATSUNAMI ,  Ryouhei KIRISAWA

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。

公开(公告)号：US20100038703A1

公开(公告)日：2010-02-18

申请号：US12501142

申请日：2009-07-10

申请人： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KITO ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

发明人： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KITO ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

IPC分类号： H01L29/792 ,  H01L27/112

CPC分类号： H01L29/792 ,  G11C5/02 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42348 ,  H01L29/7926

摘要： A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.

摘要翻译： 存储器串具有半导体层，其具有接合部分，该接合部分形成为连接相对于衬底在垂直方向上延伸的多个柱状部分和多个柱状部分的下端。 第一导电层以叠层的方式形成以包围柱状部分的侧表面和电荷存储层，并且用作存储单元的控制电极。 通过栅极绝缘膜在多个柱状部分周围形成第二导电层，并且用作选择晶体管的控制电极。 位线分别形成为与第一方向正交的第二方向作为纵向连接到多个柱状部分。