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1.发明申请公开(公告)号：US20080082793A1
公开(公告)日：2008-04-03
申请号：US11529710
申请日：2006-09-29
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/3824 , G06F9/3832 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： Apparatuses, systems, and methods for detecting and preventing write-after-write hazards, and applications thereof. In an embodiment, a load/store queue of a processor stores a first register destination value associated with a graduated load instruction. A graduation unit of the processor broadcasts a second register destination value associated with a graduating load instruction. Control logic coupled to the load/store queue and the graduation unit compares the first register destination value to the second register destination. If the first register destination value and the second register destination value match, the control logic prevents the graduated load instruction from altering an architectural state of the processor.
摘要翻译： 用于检测和防止写后危害的设备，系统和方法及其应用。 在一个实施例中，处理器的加载/存储队列存储与刻度加载指令相关联的第一寄存器目的地值。 处理器的分度单元广播与刻度加载指令相关联的第二寄存器目的地值。 耦合到加载/存储队列和毕业单元的控制逻辑将第一寄存器目的地值与第二寄存器目的地进行比较。 如果第一寄存器目的地值和第二寄存器目标值匹配，则控制逻辑防止刻度加载指令改变处理器的架构状态。
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2.发明申请Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline 审中-公开用于管理无序处理器管道中的程序计数器重定向的处理器核心和方法公开(公告)号：US20100306513A1
公开(公告)日：2010-12-02
申请号：US12794370
申请日：2010-06-04
IPC分类号： G06F9/32
CPC分类号： G06F9/3861 , G06F9/3844 , G06F9/3851 , G06F9/3855
摘要： A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.
摘要翻译： 用于在乱序处理器管线中管理程序计数器重定向的处理器核心和方法。 在一个实施例中，处理器核心的流水线包括前端指令获取部分，后端指令执行部分和流水线控制逻辑。 指令提取部分的操作与指令执行部分的操作分离。 在检测到控制传输错误预测之后，停止指令获取部分的操作，并且驻留在指令获取部分中的指令无效。 当与错误预测相关联的指令达到所选择的流水线级时，驻留在流水线的指令执行部分中的指令无效，并且重新开始从指令获取部分到处理器流水线的指令执行部分的指令流。 误用指令识别检查器和指令识别标签用于确定控制传输指令是否允许重定向指令读取。
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3.发明授权Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated 有权条件移动指令形成一个待分级的解码指令，另一个解码指令被无效公开(公告)号：US08078846B2
公开(公告)日：2011-12-13
申请号：US11640491
申请日：2006-12-18
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/384
摘要： A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.
摘要翻译： 通过形成和处理两个解码的指令以及其应用在处理器中实现的条件移动指令。 在一个实施例中，条件移动指令指定作为源和目的地的第一源操作数，第二源操作数和第三操作数。 如果第二操作数的值不等于指定值，则第一解码指令将第三操作数移动到完成缓冲寄存器。 如果第二操作数的值等于指定值，则第二解码指令将第一操作数的值移动到完成缓冲器。 当执行移动的解码指令逐渐变化时，完成缓冲寄存器的内容被传送到由第三操作数指定的寄存器文件寄存器。
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4.发明授权Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses 有权具有写连接指令的处理器中的条件分支执行和将寄存器地址与存储器地址相关联的数据移动器引擎公开(公告)号：US07721075B2
公开(公告)日：2010-05-18
申请号：US11336938
申请日：2006-01-23
IPC分类号： G06F9/40
CPC分类号： G06F9/3004 , G06F9/30098 , G06F9/30145 , G06F9/30181 , G06F9/383 , G06F9/384
摘要： A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.
摘要翻译： 具有数据移动器引擎的RISC处理器和将寄存器地址与存储器地址相关联的指令。 在一个实施例中，指令包括读取连接指令，单个写入指令，双重写入指令和解开指令。 读带，单写和双写指令用于将软件可访问寄存器地址与存储器地址相关联。 这些关联影响数据移动器引擎的操作，使得在关联的持续时间内，数据移动器引擎响应于指定移动数据到和从...移动数据的指令，将数据路由到相关联的存储器地址和处理器的执行单元 关联的寄存器地址。 本发明减少了与RISC处理器中实现程序循环相关联的指令数量和硬件开销。
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5.发明授权Processor core and method for managing branch misprediction in an out-of-order processor pipeline 有权用于在乱序处理器管线中管理分支错误预测的处理器核心和方法公开(公告)号：US07711934B2
公开(公告)日：2010-05-04
申请号：US11261654
申请日：2005-10-31
IPC分类号： G06F15/00
CPC分类号： G06F9/3861 , G06F9/3017 , G06F9/321 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3851 , G06F9/3855 , G06F9/3859
摘要： A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.
摘要翻译： 用于在乱序处理器管线中管理分支错误预测的处理器核心和方法。 在一个实施例中，处理器核心的流水线包括前端指令获取部分，后端指令执行部分和流水线控制逻辑。 指令提取部分的操作与指令执行部分的操作分离。 在检测到控制传输错误预测之后，停止指令获取部分的操作，并且驻留在指令获取部分中的指令无效。 当与错误预测相关联的指令达到所选择的流水线级时，驻留在流水线的指令执行部分中的指令无效，并且重新开始从指令获取部分到处理器流水线的指令执行部分的指令流。 误用指令识别检查器和指令识别标签用于确定控制传输指令是否允许重定向指令读取。
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公开(公告)号：US20090323535A1
公开(公告)日：2009-12-31
申请号：US12555801
申请日：2009-09-08
IPC分类号： H04L12/56
摘要： A method of distributing data across a network having a plurality of equal-cost paths. Also, a device for distributing data over a network according to the method. The data, which is typically contained in data packets, may be distributed based on at least one attribute of each of the packets. The data may also be distributed according to a weighted distribution function that allows for unequal amounts of traffic to be distributed to each of the equal-cost paths.
摘要翻译： 一种在具有多个等价路径的网络上分发数据的方法。 另外，根据该方法通过网络分发数据的设备。 通常包含在数据分组中的数据可以基于每个分组的至少一个属性来分发。 数据还可以根据加权分布函数进行分配，该加权分布函数允许将不等量的流量分配给每个等价路径。
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公开(公告)号：US20080082795A1
公开(公告)日：2008-04-03
申请号：US11640491
申请日：2006-12-18
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/384
摘要： A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.
摘要翻译： 通过形成和处理两个解码的指令以及其应用在处理器中实现的条件移动指令。 在一个实施例中，条件移动指令指定作为源和目的地的第一源操作数，第二源操作数和第三操作数。 如果第二操作数的值不等于指定值，则第一解码指令将第三操作数移动到完成缓冲寄存器。 如果第二操作数的值等于指定值，则第二解码指令将第一操作数的值移动到完成缓冲器。 当执行移动的解码指令逐渐变化时，完成缓冲寄存器的内容被传送到由第三操作数指定的寄存器文件寄存器。
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公开(公告)号：US07284076B2
公开(公告)日：2007-10-16
申请号：US10819979
申请日：2004-04-08
CPC分类号： H04L47/10 , H04L47/266 , H04L47/30 , H04L47/32
摘要： A method and a system for allocating memory in a memory buffer that is part of a data distribution device. Generally, the allocation of memory is for the purpose of storing datagrams. The method allocates memory in the buffer based, at least partially, on how ingress ports that are operably connected to the memory buffer have previously used the buffer to store datagrams. The system typically includes one or more detectors that monitor how various ingresses into the data distribution device are using and have used the memory buffer.
摘要翻译： 一种用于在作为数据分发设备的一部分的存储器缓冲器中分配存储器的方法和系统。 通常，存储器的分配是为了存储数据报的目的。 该方法至少部分地基于可操作地连接到存储器缓冲器的入口端口先前使用缓冲器来存储数据报的方式来分配缓冲器中的存储器。 系统通常包括一个或多个检测器，其监测数据分配设备中的各种入口如何使用并且已经使用存储器缓冲器。
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9.发明授权Apparatus and method for processing template based user defined instructions 有权用于处理基于模板的用户定义指令的装置和方法公开(公告)号：US08145882B1
公开(公告)日：2012-03-27
申请号：US11442696
申请日：2006-05-25
IPC分类号： G06F15/16
CPC分类号： G06F15/78 , G06F9/30181 , G06F15/16
摘要： A system implemented in hardware includes a main processing core decoding instructions for out of order execution. The instructions include template based user defined instructions. A user execution block executes the template based user defined instructions. An interface is positioned between the main processing core and the user execution block. A computer readable medium includes executable instructions to describe a processing core supporting execution of a proprietary instruction set and decoding of customized instructions that adhere to a specified pattern. The specified pattern includes a source, a destination and a latency period. A user execution block is connected to the processing core to execute the customized instructions.
摘要翻译： 在硬件中实现的系统包括用于无序执行的主处理核心解码指令。 说明包括基于模板的用户定义的指令。 用户执行块执行基于模板的用户定义的指令。 接口位于主处理核心和用户执行块之间。 计算机可读介质包括可执行指令，用于描述支持专有指令集的执行的处理核心以及遵循指定模式的定制指令的解码。 指定的模式包括源，目的地和等待时间。 用户执行块连接到处理核心以执行定制指令。
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10.发明授权Processor core and method for managing program counter redirection in an out-of-order processor pipeline 有权用于在乱序处理器管道中管理程序计数器重定向的处理器核心和方法公开(公告)号：US07734901B2
公开(公告)日：2010-06-08
申请号：US11261655
申请日：2005-10-31
IPC分类号： G06F9/32
CPC分类号： G06F9/3861 , G06F9/3844 , G06F9/3851 , G06F9/3855
摘要： A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.
摘要翻译： 用于在乱序处理器管线中管理程序计数器重定向的处理器核心和方法。 在一个实施例中，处理器核心的流水线包括前端指令获取部分，后端指令执行部分和流水线控制逻辑。 指令提取部分的操作与指令执行部分的操作分离。 在检测到控制传输错误预测之后，停止指令获取部分的操作，并且驻留在指令获取部分中的指令无效。 当与错误预测相关联的指令达到所选择的流水线级时，驻留在流水线的指令执行部分中的指令无效，并且重新开始从指令获取部分到处理器流水线的指令执行部分的指令流。 误用指令识别检查器和指令识别标签用于确定控制传输指令是否允许重定向指令读取。
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