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    Processor core and method for managing branch misprediction in an out-of-order processor pipeline
    1.
    发明授权
    Processor core and method for managing branch misprediction in an out-of-order processor pipeline 有权
    用于在乱序处理器管线中管理分​​支错误预测的处理器核心和方法

    公开(公告)号：US07711934B2

    公开(公告)日：2010-05-04

    申请号：US11261654

    申请日：2005-10-31

    申请人： Karagada Ramarao Kishore ,  Kjeld Svendsen ,  Vidya Rajagopalan

    发明人： Karagada Ramarao Kishore ,  Kjeld Svendsen ,  Vidya Rajagopalan

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3861 ,  G06F9/3017 ,  G06F9/321 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859

    摘要： A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.

    摘要翻译： 用于在乱序处理器管线中管理分​​支错误预测的处理器核心和方法。 在一个实施例中，处理器核心的流水线包括前端指令获取部分，后端指令执行部分和流水线控制逻辑。 指令提取部分的操作与指令执行部分的操作分离。 在检测到控制传输错误预测之后，停止指令获取部分的操作，并且驻留在指令获取部分中的指令无效。 当与错误预测相关联的指令达到所选择的流水线级时，驻留在流水线的指令执行部分中的指令无效，并且重新开始从指令获取部分到处理器流水线的指令执行部分的指令流。 误用指令识别检查器和指令识别标签用于确定控制传输指令是否允许重定向指令读取。

    Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
    2.
    发明授权
    Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated 有权
    条件移动指令形成一个待分级的解码指令，另一个解码指令被无效

    公开(公告)号：US08078846B2

    公开(公告)日：2011-12-13

    申请号：US11640491

    申请日：2006-12-18

    申请人： Karagada Ramarao Kishore ,  Xing Yu Jiang ,  Vidya Rajagopalan ,  Maria Ukanwa

    发明人： Karagada Ramarao Kishore ,  Xing Yu Jiang ,  Vidya Rajagopalan ,  Maria Ukanwa

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30032 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/384

    摘要： A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.

    摘要翻译： 通过形成和处理两个解码的指令以及其应用在处理器中实现的条件移动指令。 在一个实施例中，条件移动指令指定作为源和目的地的第一源操作数，第二源操作数和第三操作数。 如果第二操作数的值不等于指定值，则第一解码指令将第三操作数移动到完成缓冲寄存器。 如果第二操作数的值等于指定值，则第二解码指令将第一操作数的值移动到完成缓冲器。 当执行移动的解码指令逐渐变化时，完成缓冲寄存器的内容被传送到由第三操作数指定的寄存器文件寄存器。

    Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses
    3.
    发明授权
    Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses 有权
    具有写连接指令的处理器中的条件分支执行和将寄存器地址与存储器地址相关联的数据移动器引擎

    公开(公告)号：US07721075B2

    公开(公告)日：2010-05-18

    申请号：US11336938

    申请日：2006-01-23

    申请人： Radhika Thekkath ,  Karagada Ramarao Kishore ,  Vidya Rajagopalan ,  Kevin D. Kissell

    发明人： Radhika Thekkath ,  Karagada Ramarao Kishore ,  Vidya Rajagopalan ,  Kevin D. Kissell

    IPC分类号： G06F9/40

    CPC分类号： G06F9/3004 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/384

    摘要： A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

    摘要翻译： 具有数据移动器引擎的RISC处理器和将寄存器地址与存储器地址相关联的指令。 在一个实施例中，指令包括读取连接指令，单个写入指令，双重写入指令和解开指令。 读带，单写和双写指令用于将软件可访问寄存器地址与存储器地址相关联。 这些关联影响数据移动器引擎的操作，使得在关联的持续时间内，数据移动器引擎响应于指定移动数据到和从...移动数据的指令，将数据路由到相关联的存储器地址和处理器的执行单元 关联的寄存器地址。 本发明减少了与RISC处理器中实现程序循环相关联的指令数量和硬件开销。

    Twice issued conditional move instruction, and applications thereof
    4.
    发明申请
    Twice issued conditional move instruction, and applications thereof 有权
    两次发出条件移动指令及其应用

    公开(公告)号：US20080082795A1

    公开(公告)日：2008-04-03

    申请号：US11640491

    申请日：2006-12-18

    申请人： Karagada Ramarao Kishore ,  Xing Yu Jiang ,  Vidya Rajagopalan ,  Maria Ukanwa

    发明人： Karagada Ramarao Kishore ,  Xing Yu Jiang ,  Vidya Rajagopalan ,  Maria Ukanwa

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30032 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/384

    摘要： A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.

    摘要翻译： 通过形成和处理两个解码的指令以及其应用在处理器中实现的条件移动指令。 在一个实施例中，条件移动指令指定作为源和目的地的第一源操作数，第二源操作数和第三操作数。 如果第二操作数的值不等于指定值，则第一解码指令将第三操作数移动到完成缓冲寄存器。 如果第二操作数的值等于指定值，则第二解码指令将第一操作数的值移动到完成缓冲器。 当执行移动的解码指令逐渐变化时，完成缓冲寄存器的内容被传送到由第三操作数指定的寄存器文件寄存器。

    Processor core and method for managing branch misprediction in an out-of-order processor pipeline
    5.
    发明申请
    Processor core and method for managing branch misprediction in an out-of-order processor pipeline 有权
    用于在乱序处理器管线中管理分​​支错误预测的处理器核心和方法

    公开(公告)号：US20070101110A1

    公开(公告)日：2007-05-03

    申请号：US11261654

    申请日：2005-10-31

    申请人： Karagada Kishore ,  Kjeld Svendsen ,  Vidya Rajagopalan

    发明人： Karagada Kishore ,  Kjeld Svendsen ,  Vidya Rajagopalan

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3861 ,  G06F9/3017 ,  G06F9/321 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859

    摘要： A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing: in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.

    摘要翻译： 用于在乱序处理器管线中管理分​​支错误预测的处理器核心和方法。 在一个实施例中，处理器核心的流水线包括前端指令获取部分，后端指令执行部分和流水线控制逻辑。 指令提取部分的操作与指令执行部分的操作分离。 在检测到控制传输错误预测之后，停止指令获取部分的操作，并且驻留在指令获取部分中的指令无效。 当与错误预测相关联的指令达到所选择的流水线级时，驻留在流水线的指令执行部分中的指令无效，并且重新开始从指令获取部分到处理器流水线的指令执行部分的指令流。 误用指令识别检查器和指令识别标签用于确定控制传输指令是否允许重定向指令读取。

    Processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses
    7.
    发明申请
    Processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses 有权
    具有写入指令的处理器和将寄存器地址与存储器地址相关联的数据移动器引擎

    公开(公告)号：US20070174595A1

    公开(公告)日：2007-07-26

    申请号：US11336938

    申请日：2006-01-23

    申请人： Radhika Thekkath ,  Karagada Kishore ,  Vidya Rajagopalan

    发明人： Radhika Thekkath ,  Karagada Kishore ,  Vidya Rajagopalan

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3004 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/384

    摘要： A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

    摘要翻译： 具有数据移动器引擎的RISC处理器和将寄存器地址与存储器地址相关联的指令。 在一个实施例中，指令包括读取连接指令，单个写入指令，双重写入指令和解开指令。 读带，单写和双写指令用于将软件可访问寄存器地址与存储器地址相关联。 这些关联影响数据移动器引擎的操作，使得在关联的持续时间内，数据移动器引擎响应于指定移动数据到和从...移动数据的指令，将数据路由到相关联的存储器地址和处理器的执行单元 关联的寄存器地址。 本发明减少了与RISC处理器中实现程序循环相关联的指令数量和硬件开销。

    Low latency system bus interface for multi-master processing environments
    8.
    发明授权
    Low latency system bus interface for multi-master processing environments 有权
    用于多主处理环境的低延迟系统总线接口

    公开(公告)号：US06732208B1

    公开(公告)日：2004-05-04

    申请号：US09318551

    申请日：1999-05-27

    申请人： Adel M. Alsaadi ,  Vidya Rajagopalan

    发明人： Adel M. Alsaadi ,  Vidya Rajagopalan

    IPC分类号： G06F1300

    CPC分类号： G06F12/0831 ,  G06F12/0835

    摘要： A bus interface to a split transaction computing bus having separate address and data portions is provided. The bus interface contains separate address and data interfaces for initiating and tracking out-of-order transactions on either or both of the address or data portions of the computing bus. The bus interface includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the computing bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available. Snoop control logic is also provided to insure coherency between multiple instances of data within devices attached to the split transaction bus. Data release logic drives a data release signal on the last cycle of a data transaction to reduce latency between sequential data transactions by one or more masters on the computing bus.

    摘要翻译： 提供了具有分离的地址和数据部分的分离事务计算总线的总线接口。 总线接口包含单独的地址和数据接口，用于在计算总线的地址或数据部分的一个或两个上启动和跟踪无序事务。 总线接口包括拆分事务跟踪和控制，以为由总线接口发起的每个事务建立事务ID，并确定出现在计算总线的数据部分上的数据是否与其未完成的事务之一相关联。 总线接口还包含流控制逻辑，以确定要由总线接口读取或写入的器件是否具有可用于响应事务的资源（缓冲器）。 如果资源可用，流控制逻辑允许事务进行，并调整其计数器以反映资源的使用。 如果资源不可用，则流控制逻辑导致事务等待直到资源变得可用。 还提供了侦听控制逻辑以确保连接到拆分事务总线的设备内的数据的多个实例之间的一致性。 数据释放逻辑在数据事务的最后一个周期驱动数据释放信号，以减少计算总线上的一个或多个主器件在顺序数据事务之间的延迟。

    Data cache virtual hint way prediction, and applications thereof
    9.
    发明授权
    Data cache virtual hint way prediction, and applications thereof 有权
    数据缓存虚拟提示方式预测及其应用

    公开(公告)号：US07594079B2

    公开(公告)日：2009-09-22

    申请号：US11545706

    申请日：2006-10-11

    申请人： Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni ,  Vidya Rajagopalan

    发明人： Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni ,  Vidya Rajagopalan

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F12/0864 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/6082

    摘要： A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

    摘要翻译： 一种基于虚拟提示的数据缓存方式预测方案及其应用。 在一个实施例中，处理器基于虚拟提示值或别名方式预测值从数据高速缓存中检索数据，并且在数据的物理地址可用之前将数据转发到依赖指令。 物理地址可用后，将物理地址与转发数据的物理地址标签值进行比较，以验证转发的数据是正确的数据。 如果转发的数据是正确的数据，则产生命中信号。 如果转发的数据不是正确的数据，则会产生未命中的信号。 任何对不正确数据进行操作的指令都将被无效和/或重播。