摘要:
An adjustable gain line driver receives an input signal and a gain control signal and outputs a signal with a swing, and the swing is measured to generate a swing measurement signal. A target swing signal is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal. The swing measurement signal is compared to the target swing reference control signal and a counter generating the gain control signal is incremented until the measurement signal meets the target swing reference signal. Optionally a reset signal resets the counter, and the gain control signal, at predetermined events.
摘要:
System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.
摘要:
A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.
摘要:
System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.
摘要:
A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.
摘要:
In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.
摘要:
A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor. The impedances of the first and second transistors may be controlled by the first gate control voltage and the second gate control voltage respectively.
摘要:
A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor. The impedances of the first and second transistors may be controlled by the first gate control voltage and the second gate control voltage respectively.
摘要:
In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.
摘要:
The invention provides a method and a system for determining an end time of uplink back propagation in a mobile communication system to solve a problem of accurately judging the end time of uplink back propagation, wherein the method includes the following steps: sending data with consecutive sequence numbers in a buffer of a packet data convergence protocol (PDCP) module to a serving gateway (S-GW) via an S1 tunnel; sending data with inconsecutive sequence numbers, which is from data with a first inconsecutive sequence number to last data in the buffer of the PDCP module, to a target base station via an uplink back propagation tunnel; generating an end marker datagram; sending the end marker datagram to the target base station via the uplink back propagation tunnel; and receiving, by the target base station, the end marker datagram and determining that the uplink back propagation has ended.