公开(公告)号：US20050012524A1

公开(公告)日：2005-01-20

申请号：US10622627

申请日：2003-07-17

申请人： Michael Green ,  Nhat Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

发明人： Michael Green ,  Nhat Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

IPC分类号： H03D13/00

CPC分类号： H03D13/003

摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit asserts a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

公开(公告)号：US20050162199A1

公开(公告)日：2005-07-28

申请号：US11088152

申请日：2005-03-23

申请人： Michael Green ,  Nhat Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

发明人： Michael Green ,  Nhat Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

IPC分类号： H03D13/00 ,  H03L7/06

CPC分类号： H03D13/003

摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

摘要翻译： 与锁相环可操作地相关联的锁定检测电路指示何时将反馈时钟信号锁定到参考时钟信号。 锁定检测电路对在参考时钟周期的上升沿之间检测到的反馈时钟信号的上升沿和下降沿的数量进行计数。 锁定检测电路对在其中检测到反馈时钟信号的单个上升沿和单个下降沿的参考时钟信号的连续有效周期的数量进行计数。 当连续的有效周期数超过预定数量时，锁定检测电路使用状态机来声明锁定信号。 如果锁定检测电路指示锁定信号，然后检测到无效的参考时钟周期，则如果下一个参考时钟周期相对于偏斜反馈时钟信号有效，锁定检测电路将继续指示锁定。

公开(公告)号：US20100150290A1

公开(公告)日：2010-06-17

申请号：US12710250

申请日：2010-02-22

申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

IPC分类号： H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的停止逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。 在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。

公开(公告)号：US20050069071A1

公开(公告)日：2005-03-31

申请号：US10675027

申请日：2003-09-30

申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

IPC分类号： H03L7/081 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的失调逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。 在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。

公开(公告)号：US08130891B2

公开(公告)日：2012-03-06

申请号：US12710250

申请日：2010-02-22

申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

IPC分类号： H03D3/24

CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的失调逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。 在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。

公开(公告)号：US07668271B2

公开(公告)日：2010-02-23

申请号：US10675027

申请日：2003-09-30

申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

IPC分类号： H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，该电路包括一个与第一，第二和第三级耦合的稳态逻辑，并能够响应第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，电路包括停顿逻辑，指示器和计数器。 在本发明的第五实施例中，电路包括平均电路，用于响应于在预定时间段内对第一和第二调整信号的平均来输出相位调整信号。

公开(公告)号：US06879195B2

公开(公告)日：2005-04-12

申请号：US10622627

申请日：2003-07-17

申请人： Michael Green ,  Nhat M. Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

发明人： Michael Green ,  Nhat M. Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

IPC分类号： H03D13/00 ,  H03L7/06

CPC分类号： H03D13/003

摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit asserts a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

摘要翻译： 与锁相环可操作地相关联的锁定检测电路指示何时将反馈时钟信号锁定到参考时钟信号。 锁定检测电路对在参考时钟周期的上升沿之间检测到的反馈时钟信号的上升沿和下降沿的数量进行计数。 锁定检测电路对在其中检测到反馈时钟信号的单个上升沿和单个下降沿的参考时钟信号的连续有效周期的数量进行计数。 当连续的有效周期数超过预定数量时，锁定检测电路断言锁定信号。 如果锁定检测电路指示锁定信号，然后检测到无效的参考时钟周期，则如果下一个参考时钟周期相对于偏斜反馈时钟信号有效，锁定检测电路将继续指示锁定。

公开(公告)号：US07084681B2

公开(公告)日：2006-08-01

申请号：US11088152

申请日：2005-03-23

申请人： Michael Green ,  Nhat M. Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

发明人： Michael Green ,  Nhat M. Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

IPC分类号： H03L7/06

CPC分类号： H03D13/003

摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, the lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

摘要翻译： 与锁相环可操作地相关联的锁定检测电路指示何时将反馈时钟信号锁定到参考时钟信号。 锁定检测电路对在参考时钟周期的上升沿之间检测到的反馈时钟信号的上升沿和下降沿的数量进行计数。 锁定检测电路对在其中检测到反馈时钟信号的单个上升沿和单个下降沿的参考时钟信号的连续有效周期的数量进行计数。 当连续的有效周期数超过预定数量时，锁定检测电路使用状态机来声明锁定信号。 如果锁定检测电路指示锁定信号，然后检测到无效的参考时钟周期，则如果下一个参考时钟周期相对于偏斜反馈时钟信号有效，则锁定检测电路继续指示锁定。

公开(公告)号：US20050189961A1

公开(公告)日：2005-09-01

申请号：US11058088

申请日：2005-02-15

申请人： Yohan Frans ,  Nhat Nguyen ,  Yueyong Wang

发明人： Yohan Frans ,  Nhat Nguyen ,  Yueyong Wang

IPC分类号： H03K5/00 ,  H03K5/003 ,  H03K5/01 ,  H03K19/003 ,  H03K19/0175 ,  H04L25/02

CPC分类号： H04L25/0292 ,  H03K5/003 ,  H04L25/0272

摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.

公开(公告)号：US20050168292A1

公开(公告)日：2005-08-04

申请号：US11084438

申请日：2005-03-17

申请人： Yohan Frans ,  Nhat Nguyen

发明人： Yohan Frans ,  Nhat Nguyen

IPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/093 ,  H03L7/00

CPC分类号： H03L7/0896 ,  H03L7/0812 ,  H03L7/093

摘要： A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage across the replication capacitor is proportional to the control voltage of a voltage-controlled oscillator of the compensating phase-locked loop. A second embodiment generates the compensation current by controlling the voltage on the gate of a transistor. The gate voltage depends on charge added and subtracted by a charge pump in addition to the charge pumps in the loop filter. A third embodiment applies a leakage compensation circuit to a delay locked loop.

摘要翻译： 补偿锁相环的环路滤波器包含由具有薄栅极氧化物介电层的晶体管形成的电容器。 泄漏电流通过电容器泄漏。 为了避免由漏电流引起的锁相环的输出信号中的抖动，提供了泄漏补偿电路。 第一实施例的漏电补偿电路使用复制电容器和电流镜复制泄漏电流。 复制电容器两端的电压与补偿锁相环的压控振荡器的控制电压成比例。 第二实施例通过控制晶体管的栅极上的电压来产生补偿电流。 除了环路滤波器中的电荷泵之外，栅极电压还取决于电荷泵的电荷和扣除电荷。 第三实施例将泄漏补偿电路应用于延迟锁定环路。