公开(公告)号：US06879195B2

公开(公告)日：2005-04-12

申请号：US10622627

申请日：2003-07-17

申请人： Michael Green ,  Nhat M. Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

发明人： Michael Green ,  Nhat M. Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

IPC分类号： H03D13/00 ,  H03L7/06

CPC分类号： H03D13/003

摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit asserts a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

摘要翻译： 与锁相环可操作地相关联的锁定检测电路指示何时将反馈时钟信号锁定到参考时钟信号。 锁定检测电路对在参考时钟周期的上升沿之间检测到的反馈时钟信号的上升沿和下降沿的数量进行计数。 锁定检测电路对在其中检测到反馈时钟信号的单个上升沿和单个下降沿的参考时钟信号的连续有效周期的数量进行计数。 当连续的有效周期数超过预定数量时，锁定检测电路断言锁定信号。 如果锁定检测电路指示锁定信号，然后检测到无效的参考时钟周期，则如果下一个参考时钟周期相对于偏斜反馈时钟信号有效，锁定检测电路将继续指示锁定。

公开(公告)号：US07084681B2

公开(公告)日：2006-08-01

申请号：US11088152

申请日：2005-03-23

申请人： Michael Green ,  Nhat M. Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

发明人： Michael Green ,  Nhat M. Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

IPC分类号： H03L7/06

CPC分类号： H03D13/003

摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, the lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

摘要翻译： 与锁相环可操作地相关联的锁定检测电路指示何时将反馈时钟信号锁定到参考时钟信号。 锁定检测电路对在参考时钟周期的上升沿之间检测到的反馈时钟信号的上升沿和下降沿的数量进行计数。 锁定检测电路对在其中检测到反馈时钟信号的单个上升沿和单个下降沿的参考时钟信号的连续有效周期的数量进行计数。 当连续的有效周期数超过预定数量时，锁定检测电路使用状态机来声明锁定信号。 如果锁定检测电路指示锁定信号，然后检测到无效的参考时钟周期，则如果下一个参考时钟周期相对于偏斜反馈时钟信号有效，则锁定检测电路继续指示锁定。

公开(公告)号：US20050012524A1

公开(公告)日：2005-01-20

申请号：US10622627

申请日：2003-07-17

申请人： Michael Green ,  Nhat Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

发明人： Michael Green ,  Nhat Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

IPC分类号： H03D13/00

CPC分类号： H03D13/003

摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit asserts a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

公开(公告)号：US20050162199A1

公开(公告)日：2005-07-28

申请号：US11088152

申请日：2005-03-23

申请人： Michael Green ,  Nhat Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

发明人： Michael Green ,  Nhat Nguyen ,  Yohan Frans ,  Dennis Kim ,  Todd Bystrom

IPC分类号： H03D13/00 ,  H03L7/06

CPC分类号： H03D13/003

摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

摘要翻译： 与锁相环可操作地相关联的锁定检测电路指示何时将反馈时钟信号锁定到参考时钟信号。 锁定检测电路对在参考时钟周期的上升沿之间检测到的反馈时钟信号的上升沿和下降沿的数量进行计数。 锁定检测电路对在其中检测到反馈时钟信号的单个上升沿和单个下降沿的参考时钟信号的连续有效周期的数量进行计数。 当连续的有效周期数超过预定数量时，锁定检测电路使用状态机来声明锁定信号。 如果锁定检测电路指示锁定信号，然后检测到无效的参考时钟周期，则如果下一个参考时钟周期相对于偏斜反馈时钟信号有效，锁定检测电路将继续指示锁定。

公开(公告)号：US08130891B2

公开(公告)日：2012-03-06

申请号：US12710250

申请日：2010-02-22

申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

IPC分类号： H03D3/24

CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的失调逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。 在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。

公开(公告)号：US07668271B2

公开(公告)日：2010-02-23

申请号：US10675027

申请日：2003-09-30

申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

IPC分类号： H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，该电路包括一个与第一，第二和第三级耦合的稳态逻辑，并能够响应第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，电路包括停顿逻辑，指示器和计数器。 在本发明的第五实施例中，电路包括平均电路，用于响应于在预定时间段内对第一和第二调整信号的平均来输出相位调整信号。

公开(公告)号：US20100150290A1

公开(公告)日：2010-06-17

申请号：US12710250

申请日：2010-02-22

申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

IPC分类号： H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的停止逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。 在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。

公开(公告)号：US20050069071A1

公开(公告)日：2005-03-31

申请号：US10675027

申请日：2003-09-30

申请人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

发明人： Dennis Kim ,  Jason Wei ,  Yohan Frans ,  Todd Bystrom ,  Nhat Nguyen ,  Kevin Donnelly

IPC分类号： H03L7/081 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/091 ,  H04L7/0331

摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

摘要翻译： 诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的失调逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。 在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。

公开(公告)号：US09036436B2

公开(公告)日：2015-05-19

申请号：US13982474

申请日：2012-05-03

申请人： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

发明人： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

IPC分类号： G11C7/22 ,  G11C29/02 ,  G06F1/10

CPC分类号： G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

摘要翻译： 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

公开(公告)号：US20050154817A1

公开(公告)日：2005-07-14

申请号：US11030382

申请日：2005-01-06

申请人： Richard Barth ,  Ely Tsern ,  Craig Hampel ,  Frederick Ware ,  Todd Bystrom ,  Bradley May ,  Paul Davis

发明人： Richard Barth ,  Ely Tsern ,  Craig Hampel ,  Frederick Ware ,  Todd Bystrom ,  Bradley May ,  Paul Davis

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076

CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02D10/151

摘要： A method of operation of a memory device and system includes receiving a first and second value in embodiments. The first value is representative of a number of clock cycles of a clock signal that elapse between latching a column address and an access of data sensed from a row of memory cells in a memory array. A location of the data is based on the column address. The second value is representative of a number of clock cycles of the clock signal that elapse between the access of data from the memory array and outputting the data. The first and second values are received during an initialization sequence. Information in units of time that represents first and second timing parameters that pertains to the memory device is read from a storage location. The information that represents the first and second timing parameters are then converted from units of time to units of clock cycles to derive the first and second values.

摘要翻译： 存储器件和系统的操作方法包括在实施例中接收第一和第二值。 第一个值表示在锁存列地址和从存储器阵列中的一行存储器单元传感的数据的访问之间经过的时钟信号的多个时钟周期。 数据的位置基于列地址。 第二个值表示从存储器阵列访问数据并输出数据之间经过的时钟信号的数个时钟周期。 在初始化序列期间接收第一和第二值。 从存储位置读取表示与存储器件相关的第一和第二定时参数的以时间为单位的信息。 然后将表示第一和第二定时参数的信息从时间单位从时钟周期的单位转换为导出第一和第二值。