公开(公告)号：US06920059B2

公开(公告)日：2005-07-19

申请号：US10065921

申请日：2002-11-29

申请人： Michael Jacob ,  Thomas Roehr ,  Norbert Rehm ,  Daisaburo Takashima

发明人： Michael Jacob ,  Thomas Roehr ,  Norbert Rehm ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

摘要翻译： 公开了一种减少存储器阵列中的噪声耦合的方法。 存储器阵列包括通过字线，位线和平行线互连的多个存储器单元。 存储单元被布置成具有耦合到读出放大器的第一和第二位线的列。 在存储器访问期间，至少相邻的位线对不被激活。 选定的位线对或对配有一条平行线脉冲。

公开(公告)号：US06731529B2

公开(公告)日：2004-05-04

申请号：US10161907

申请日：2002-06-04

申请人： Michael Jacob ,  Joerg Wohlfahrt ,  Norbert Rehm ,  Daisaburo Takashima

发明人： Michael Jacob ,  Joerg Wohlfahrt ,  Norbert Rehm ,  Daisaburo Takashima

IPC分类号： G11C1122

CPC分类号： H01L27/11502 ,  H01L27/108 ,  H01L27/10814

摘要： A memory chain with capacitors having different capacitances, depending on the location of the memory cell within the chain, is described. Varying the capacitances of the capacitors advantageously enables an effective capacitance for all memory cells within the chain to be about the same.

摘要翻译： 描述了具有不同电容的电容器的存储器链，这取决于链中存储器单元的位置。 改变电容器的电容有利地使链中所有存储单元的有效电容大致相同。

公开(公告)号：US07092304B2

公开(公告)日：2006-08-15

申请号：US10931978

申请日：2004-09-02

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Thomas Roehr

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Thomas Roehr

IPC分类号： G11C7/04

CPC分类号： G11C7/14 ,  G03B42/02 ,  G11C7/04 ,  G11C11/22

摘要： A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.

摘要翻译： 虚拟电容器驱动电位VDC被提供给虚拟电容器的一个电极，并且在其另一个电极中产生用于确定存储器单元的数据值的参考电位。 用于产生电位VDC的潜在发电机电路由输出具有温度依赖性的电位VBGRTEMP的BGR电路和串联连接在BGR电路的输出端子与接地点之间的电阻器R 3和R 4构成。 从电阻器R 3和R 4的连接点输出电位VDC。 电阻VDC的温度依赖性根据电阻器R 1 - 1，R 1 - 2和R 2的电阻比进行调整，并且绝对值根据电阻器R 3和R 4的电阻比进行调整。

公开(公告)号：US07127598B2

公开(公告)日：2006-10-24

申请号：US10322587

申请日：2002-12-19

申请人： Kohei Oikawa ,  Shinichiro Shiratake ,  Yoshiaki Takeuchi ,  Daisaburo Takashima ,  Thomas Roehr

发明人： Kohei Oikawa ,  Shinichiro Shiratake ,  Yoshiaki Takeuchi ,  Daisaburo Takashima ,  Thomas Roehr

IPC分类号： G06F15/177

CPC分类号： G06F1/24

摘要： A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.

摘要翻译： 半导体器件包括内部电源，至少一个半导体电路块，延迟电路和检测电路。 初始化时，内部电源输出初始化完成信号。 半导体电路块基于由内部电源产生的电压进行工作。 延迟电路延迟初始化完成信号。 检测电路响应于由延迟电路延迟的初始化完成信号和外部输入的第一输入信号，命令半导体电路块开始操作。

公开(公告)号：US06707736B2

公开(公告)日：2004-03-16

申请号：US10165277

申请日：2002-06-10

申请人： Tadashi Miyakawa ,  Daisaburo Takashima ,  Thomas Roehr

发明人： Tadashi Miyakawa ,  Daisaburo Takashima ,  Thomas Roehr

IPC分类号： G11C700

CPC分类号： G11C29/50012 ,  G11C7/22 ,  G11C29/50

摘要： A semiconductor memory device includes a memory cell array, a plurality of input/output terminals to input cell data written to the memory cell array and output cell data read from the memory cell array, a test mode setting circuit which sets a test mode to monitor a plurality of timing signals which control input/output operation timing of the cell data, and switch circuits connected to the plurality of input/output terminals. The switch circuits simultaneously output the plurality of timing signals from the plurality of input/output terminals in the test mode.

摘要翻译： 半导体存储器件包括存储单元阵列，多个输入/输出端子，用于输入写入存储单元阵列的单元数据并输出从存储单元阵列读出的单元数据;测试模式设置电路，其将测试模式设置为监视 控制单元数据的输入/输出操作定时的多个定时信号，以及连接到多个输入/输出端子的开关电路。 开关电路在测试模式下同时输出来自多个输入/输出端子的多个定时信号。

公开(公告)号：US20050276140A1

公开(公告)日：2005-12-15

申请号：US10931978

申请日：2004-09-02

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Thomas Roehr

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Thomas Roehr

IPC分类号： G11C11/22 ,  G03B42/02 ,  G03C5/16 ,  G11C7/04 ,  G11C7/14

CPC分类号： G11C7/14 ,  G03B42/02 ,  G11C7/04 ,  G11C11/22

摘要： A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.

摘要翻译： 虚拟电容器驱动电位VDC被提供给虚拟电容器的一个电极，并且在其另一个电极中产生用于确定存储器单元的数据值的参考电位。 用于产生电位VDC的潜在发电机电路由输出具有温度依赖性的电位VBGRTEMP的BGR电路和串联连接在BGR电路的输出端子与接地点之间的电阻器R 3和R 4构成。 从电阻器R 3和R 4的连接点输出电位VDC。 电阻VDC的温度依赖性根据电阻器R 1 - 1，R 1 - 2和R 2的电阻比进行调整，并且绝对值根据电阻器R 3和R 4的电阻比进行调整。

公开(公告)号：US06898104B2

公开(公告)日：2005-05-24

申请号：US10291610

申请日：2002-11-12

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Michael Jacob

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Michael Jacob

IPC分类号： G11C7/06 ,  G11C11/22

CPC分类号： G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C11/22

摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

摘要翻译： 半导体器件包括存储单元阵列，与位线互补的位线/ /位线，参考电压产生电路和读出放大器。 位线连接到存储器单元并且被施加从存储单元阵列的每个存储单元读取的电压。 /位线提供参考电压。 参考电压产生电路产生具有温度依赖性的参考电压，用于补偿由温度读取到位线的电压变化。 参考电压产生电路控制参考电压，使得参考电压采取指示“0”数据的信号值分布的轨迹的中点和指示“1”数据的信号值分布。 读出放大器将读取到位线的电压与提供给/位线的参考电压进行比较，并放大它们之间的差值。

公开(公告)号：US20050146918A1

公开(公告)日：2005-07-07

申请号：US11059569

申请日：2005-02-17

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Michael Jacob

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Michael Jacob

IPC分类号： G11C7/06 ,  G11C11/22

CPC分类号： G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C11/22

摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

公开(公告)号：US07142473B2

公开(公告)日：2006-11-28

申请号：US11059569

申请日：2005-02-17

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Michael Jacob

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Michael Jacob

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C11/22

摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

摘要翻译： 半导体器件包括存储单元阵列，与位线互补的位线/ /位线，参考电压产生电路和读出放大器。 位线连接到存储器单元并且被施加从存储单元阵列的每个存储单元读取的电压。 /位线提供参考电压。 参考电压产生电路产生具有温度依赖性的参考电压，用于补偿由温度读取到位线的电压变化。 参考电压产生电路控制参考电压，使得参考电压采取指示“0”数据的信号值分布的轨迹的中点和指示“1”数据的信号值分布。 读出放大器将读取到位线的电压与提供给/位线的参考电压进行比较，并放大它们之间的差值。

公开(公告)号：US08792266B2

公开(公告)日：2014-07-29

申请号：US13605674

申请日：2012-09-06

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： A memory cell is formed with a resistance variable element, which is interposed between first and second electrodes and can store resistance changes representing 2 or more different values, and first and second cell transistors having source terminals thereof connected to the first electrode, and gates thereof to a word line. A drain of the first cell transistor is connected to a bit line, and a drain of the second cell transistor is connected to a data line. The second electrode is connected to a source line. During a read operation, the first and second cell transistors are kept in an ON state, and a current is supplied from the bit line to the source line through the memory cell. Data is read according to the electrical potential difference between the data line and the source line.

摘要翻译： 存储单元形成有电阻可变元件，其被插入在第一和第二电极之间，并且可以存储表示2个或更多个不同值的电阻变化，以及其源极端子连接到第一电极的第一和第二单元晶体管及其栅极 到一个字线。 第一单元晶体管的漏极连接到位线，并且第二单元晶体管的漏极连接到数据线。 第二电极连接到源极线。 在读取操作期间，第一和第二单元晶体管保持在导通状态，并且通过存储单元从位线向源极线提供电流。 根据数据线和源极线之间的电位差读取数据。