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    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
    2.
    发明授权
    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
    用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构

    公开(公告)号：US06936512B2

    公开(公告)日：2005-08-30

    申请号：US10260085

    申请日：2002-09-27

    申请人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    发明人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/8242

    CPC分类号： H01L29/66181 ,  H01L21/3144 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10864 ,  H01L27/10867

    摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.

    摘要翻译： 本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。 所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。 然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸 。 然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极 使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。 在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。

    Process flow for capacitance enhancement in a DRAM trench
    4.
    发明授权
    Process flow for capacitance enhancement in a DRAM trench 失效
    DRAM沟槽中电容增强的工艺流程

    公开(公告)号：US06555430B1

    公开(公告)日：2003-04-29

    申请号：US09723420

    申请日：2000-11-28

    申请人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

    发明人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/964

    摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

    摘要翻译： 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

    Diagnosing in-line critical dimension control adjustments using optical proximity correction verification
    5.
    发明授权
    Diagnosing in-line critical dimension control adjustments using optical proximity correction verification 失效
    使用光学邻近校正验证诊断在线临界尺寸控制调整

    公开(公告)号：US08577489B2

    公开(公告)日：2013-11-05

    申请号：US13014152

    申请日：2011-01-26

    申请人： James A. Bruce ,  Kenneth T. Settlemyer, Jr.

    发明人： James A. Bruce ,  Kenneth T. Settlemyer, Jr.

    IPC分类号： G06F19/00

    CPC分类号： G03F1/36 ,  G03F1/70 ,  G03F7/705

    摘要： Solutions for diagnosing in-line critical dimension control adjustments in a lithographic process are disclosed. In one embodiment, a method includes: locating a control structure in a data set representing one of a chip or a kerf; simulating component dimensions within a region proximate to the control structure; determining a difference between the simulated component dimensions within the region and target component dimensions within the region; determining whether the difference exceeds a predetermined tolerance threshold; adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.

    摘要翻译： 公开了用于诊断光刻工艺中的在线临界尺寸控制调整的解决方案。 在一个实施例中，一种方法包括：将控制结构定位在表示芯片或切口之一的数据集中; 在靠近控制结构的区域内模拟部件尺寸; 确定区域内的模拟部件尺寸与该区域内的目标部件尺寸之间的差异; 确定所述差异是否超过预定的容差阈值; 响应于确定所述差异来调整模拟条件超过所述预定公差阈值; 并且响应于所述模拟条件的调整，重复所述区域内的所述分量尺寸的模拟，所述差的确定以及所述差是否超过所述预定公差阈值。

    Pattern enhancement by crystallographic etching
    6.
    发明授权
    Pattern enhancement by crystallographic etching 有权
    通过晶体蚀刻的图案增强

    公开(公告)号：US07390745B2

    公开(公告)日：2008-06-24

    申请号：US11162800

    申请日：2005-09-23

    申请人： Thomas W. Dyer ,  Kenneth T. Settlemyer, Jr. ,  James J. Toomey ,  Haining Yang

    发明人： Thomas W. Dyer ,  Kenneth T. Settlemyer, Jr. ,  James J. Toomey ,  Haining Yang

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/30608 ,  H01L21/32134

    摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

    摘要翻译： 与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

    Device fabrication by anisotropic wet etch
    7.
    发明授权
    Device fabrication by anisotropic wet etch 失效
    通过各向异性湿法蚀刻的器件制造

    公开(公告)号：US07696539B2

    公开(公告)日：2010-04-13

    申请号：US12141878

    申请日：2008-06-18

    申请人： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

    发明人： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

    IPC分类号： H01L29/80

    CPC分类号： H01L21/84 ,  H01L21/30608 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/66818 ,  H01L29/785

    摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

    摘要翻译： 提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。 产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。 用包含氢氧化铵的各向异性溶液湿式蚀刻基座。 基座的侧壁变小，在基座上形成截面减小的部分。 选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

    Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same
    8.
    发明授权
    Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same 有权
    用于蚀刻对非晶/多晶半导体有选择性的单晶半导体及其结构的方法

    公开(公告)号：US07563670B2

    公开(公告)日：2009-07-21

    申请号：US11558974

    申请日：2006-11-13

    申请人： Kangguo Cheng ,  Richard O. Henry ,  Kenneth T. Settlemyer, Jr.

    发明人： Kangguo Cheng ,  Richard O. Henry ,  Kenneth T. Settlemyer, Jr.

    IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/20

    CPC分类号： H01L21/32134 ,  H01L21/30608 ,  H01L27/10841 ,  H01L27/10864

    摘要： A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

    摘要翻译： 一种形成垂直DRAM装置的方法。 下沟槽填充有用于电容器的多晶或非晶半导体。 上沟槽部分具有暴露的单晶半导体的侧壁。 该方法然后包括蚀刻单晶半导体侧壁以将上部沟槽部分加宽超过电容器的半导体填充物的暴露的上表面，以在邻近暴露的上部沟槽的上部沟槽的底部上形成单晶半导体的暴露区域 半导体填料的上表面。 沟槽顶部绝缘层沉积在上沟槽的底部上方，半导体填充物的上表面和相邻的单晶半导体区域之上。 该方法然后包括形成垂直栅极电介质层，其中沟槽顶部绝缘层延伸到垂直栅极绝缘层下方。

    Method of fabricating a bottle trench and a bottle trench capacitor
    9.
    发明授权
    Method of fabricating a bottle trench and a bottle trench capacitor 有权
    制造瓶沟槽和瓶槽电容器的方法

    公开(公告)号：US07122439B2

    公开(公告)日：2006-10-17

    申请号：US10904582

    申请日：2004-11-17

    申请人： Oh-Jung Kwon ,  Kenneth T. Settlemyer, Jr. ,  Ravikumar Ramachandran ,  Min-Soo Kim

    发明人： Oh-Jung Kwon ,  Kenneth T. Settlemyer, Jr. ,  Ravikumar Ramachandran ,  Min-Soo Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1087 ,  H01L29/66181

    摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

    摘要翻译： 制造瓶沟槽和瓶沟电容器的方法。 该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。

    Vertical hard mask
    10.
    发明授权
    Vertical hard mask 失效
    垂直硬面罩

    公开(公告)号：US06723611B2

    公开(公告)日：2004-04-20

    申请号：US10241225

    申请日：2002-09-10

    申请人： Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Helmut Horst Tews ,  Kenneth T. Settlemyer, Jr.

    发明人： Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Helmut Horst Tews ,  Kenneth T. Settlemyer, Jr.

    IPC分类号： H01L2120

    CPC分类号： H01L27/1087

    摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.

    摘要翻译： 在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在 下部。