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208 条记录 (耗时 0.033 秒)

    Vertical hard mask
    2.
    发明授权
    Vertical hard mask 失效
    垂直硬面罩

    公开(公告)号：US06723611B2

    公开(公告)日：2004-04-20

    申请号：US10241225

    申请日：2002-09-10

    申请人： Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Helmut Horst Tews ,  Kenneth T. Settlemyer, Jr.

    发明人： Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Helmut Horst Tews ,  Kenneth T. Settlemyer, Jr.

    IPC分类号： H01L2120

    CPC分类号： H01L27/1087

    摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.

    摘要翻译： 在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在 下部。

    Pitcher-shaped active area for field effect transistor and method of forming same
    3.
    发明授权
    Pitcher-shaped active area for field effect transistor and method of forming same 失效
    投币型场效应晶体管及其形成方法

    公开(公告)号：US06960514B2

    公开(公告)日：2005-11-01

    申请号：US10803395

    申请日：2004-03-18

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

    摘要翻译： 对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。 投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。 还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部 区域结构。 本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

    High performance logic and high density embedded dram with borderless contact and antispacer
    4.
    发明授权
    High performance logic and high density embedded dram with borderless contact and antispacer 失效
    高性能逻辑和高密度嵌入式电脑，无边界接触和对抗

    公开(公告)号：US06709926B2

    公开(公告)日：2004-03-23

    申请号：US10160540

    申请日：2002-05-31

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce Bennett Doris ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Jack Allan Mandelman

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce Bennett Doris ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Jack Allan Mandelman

    IPC分类号： H01L21336

    CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10891 ,  H01L27/10894

    摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.

    摘要翻译： 集成电路包括具有以最小光刻特征尺寸分隔的阵列晶体管的存储单元，以及由扩散阻挡层封装的非硅化金属位线，而高性能逻辑晶体管可以形成在同一芯片上，而不会损害性能，包括有效沟道硅化触点低 源极/漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅极电介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。 该结构通过易平坦化的材料实现，并且使用平坦化为不同材料的结构的高度的类似掩模来去耦合逻辑晶体管中的衬底和栅极注入。

    Semi-insulating diffusion barrier for low-resistivity gate conductors
    5.
    发明授权
    Semi-insulating diffusion barrier for low-resistivity gate conductors 失效
    用于低电阻率栅极导体的半绝缘扩散阻挡层

    公开(公告)号：US06444516B1

    公开(公告)日：2002-09-03

    申请号：US09613197

    申请日：2000-07-07

    申请人： Lawrence Alfred Clevenger ,  Jack A. Mandelman ,  Rajarao Jammy ,  Oleg Gluschenkov ,  Irene Lennox McStay ,  Kwong Hon Wong ,  Johnathan Faltermeier

    发明人： Lawrence Alfred Clevenger ,  Jack A. Mandelman ,  Rajarao Jammy ,  Oleg Gluschenkov ,  Irene Lennox McStay ,  Kwong Hon Wong ,  Johnathan Faltermeier

    IPC分类号： H01L218234

    CPC分类号： H01L21/28044 ,  H01L29/4941

    摘要： A gate structure for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer on a semiconductor substrate, over which a polysilicon gate electrode is formed. The gate structure further includes a gate conductor that is electrically connected with the gate electrode through a diffusion barrier layer having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.

    摘要翻译： 用于半导体器件的栅极结构，特别是用于诸如CMOS技术的应用的MOSFET。 栅结构需要在半导体衬底上形成电绝缘层，形成多晶硅栅电极。 栅极结构还包括通过具有半绝缘性质的扩散阻挡层与栅电极电连接的栅极导体。 调整扩散阻挡层的组成和厚度，使得阻挡层有效地阻挡栅极导体和多晶硅栅电极之间的扩散和混合，但提供足够的电容耦合和/或电流泄漏，从而不显着增加栅极 门结构的传播延迟。

    High performance logic and high density embedded dram with borderless contact and antispacer
    6.
    发明授权
    High performance logic and high density embedded dram with borderless contact and antispacer 失效
    高性能逻辑和高密度嵌入式电脑，无边界接触和对抗

    公开(公告)号：US06873010B2

    公开(公告)日：2005-03-29

    申请号：US10682430

    申请日：2003-10-10

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce Bennett Doris ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Jack Allen Mandelman

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce Bennett Doris ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Jack Allen Mandelman

    IPC分类号： H01L21/8242 ,  H01L29/76

    CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10891 ,  H01L27/10894

    摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.

    摘要翻译： 集成电路包括具有由最小光刻特征分隔的阵列晶体管和由扩散阻挡层封装的非硅化金属位线的存储单元，而高性能逻辑晶体管可以形成在同一芯片上而不损害包括有效通道在内的性能， /漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。 该结构通过使用掩模或抗间隔物（优选易于平坦化的材料）开发不同材料的厚/高结构来实现，并且使用平坦化为不同材料的结构的高度的类似掩模以使基板和栅极注入分离 在逻辑晶体管中。