公开(公告)号：US09075421B2

公开(公告)日：2015-07-07

申请号：US14116785

申请日：2011-05-27

申请人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

发明人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

IPC分类号： G05F1/46 ,  G06F1/26

CPC分类号： G05F1/46 ,  G06F1/26

摘要： An integrated circuit device comprising at least one voltage supply module arranged to receive at an input thereof at least one control signal and to provide at an output thereof a voltage signal in accordance with the received at least one control signal, and at least one control module comprising at least one feedback loop between the output of the at least one voltage supply module and the input of the at least one voltage supply module, and arranged to generate the at least one control signal based at least partly on the voltage level of the voltage signal output by the at least one voltage supply module. The at least one control module is further arranged to receive at an input thereof at least one instantaneous indication of a load current at the output of the at least one voltage supply module, and apply a compensation to the at least one control signal provided to the at least one voltage supply module based at least partly on the received at least one indication of the load current.

摘要翻译： 一种集成电路装置，包括至少一个电压供应模块，其布置成在其输入处接收至少一个控制信号，并在其输出端提供根据所接收的至少一个控制信号的电压信号，以及至少一个控制模块 包括在所述至少一个电压供应模块的输出和所述至少一个电压供应模块的输入之间的至少一个反馈环路，并被布置成至少部分地基于所述电压的电压电平来产生所述至少一个控制信号 信号由所述至少一个电压供应模块输出。 所述至少一个控制模块还被布置成在其输入处接收至少一个电压供应模块的输出处的负载电流的至少一个瞬时指示，并且向提供给所述至少一个电压供应模块的至少一个控制信号施加补偿 至少一个电压供应模块至少部分地基于接收到的负载电流的至少一个指示。

公开(公告)号：US20150204917A1

公开(公告)日：2015-07-23

申请号：US14415151

申请日：2012-07-19

申请人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

发明人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

IPC分类号： G01R19/10 ,  G01R31/28

CPC分类号： G01R19/10 ,  G01R31/2856

摘要： A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.

摘要翻译： 用于通过装置上的片上电压差测量的系统包括：第一压控振荡器电路，具有可连接到通过装置的第一端子的第一电压控制输入; 第二压控振荡器电路，具有可连接到通过装置的第二端子的第二电压控制输入; 第一计数器电路，被布置成对来自第一压控振荡器电路的第一输出信号的振荡周期进行计数，并且当计数第一输出信号的预定数量的振荡周期时提供停止信号; 以及第二计数器电路，被布置成对来自第二压控振荡器电路的第二输出信号的振荡周期进行计数，并根据停止信号停止计数。

公开(公告)号：US09500679B2

公开(公告)日：2016-11-22

申请号：US14415151

申请日：2012-07-19

申请人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

发明人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

IPC分类号： G01F15/06 ,  G01R19/10 ,  G01R31/28

CPC分类号： G01R19/10 ,  G01R31/2856

摘要： A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.

公开(公告)号：US20140176220A1

公开(公告)日：2014-06-26

申请号：US14116785

申请日：2011-05-27

申请人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

发明人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

IPC分类号： G05F1/46

CPC分类号： G05F1/46 ,  G06F1/26

摘要： An integrated circuit device comprising at least one voltage supply module arranged to receive at an input thereof at least one control signal and to provide at an output thereof a voltage signal in accordance with the received at least one control signal, and at least one control module comprising at least one feedback loop between the output of the at least one voltage supply module and the input of the at least one voltage supply module, and arranged to generate the at least one control signal based at least partly on the voltage level of the voltage signal output by the at least one voltage supply module. The at least one control module is further arranged to receive at an input thereof at least one instantaneous indication of a load current at the output of the at least one voltage supply module, and apply a compensation to the at least one control signal provided to the at least one voltage supply module based at least partly on the received at least one indication of the load current.

摘要翻译： 一种集成电路装置，包括至少一个电压供应模块，其布置成在其输入处接收至少一个控制信号，并在其输出端提供根据所接收的至少一个控制信号的电压信号，以及至少一个控制模块 包括在所述至少一个电压供应模块的输出和所述至少一个电压供应模块的输入之间的至少一个反馈环路，并被布置成至少部分地基于所述电压的电压电平来产生所述至少一个控制信号 信号由所述至少一个电压供应模块输出。 所述至少一个控制模块还被布置成在其输入处接收至少一个电压供应模块的输出处的负载电流的至少一个瞬时指示，并且向提供给所述至少一个电压供应模块的至少一个控制信号施加补偿 至少一个电压供应模块至少部分地基于接收到的负载电流的至少一个指示。

公开(公告)号：US09092163B2

公开(公告)日：2015-07-28

申请号：US13510103

申请日：2009-11-30

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： G06F1/12 ,  G06F13/42 ,  G11C7/10

CPC分类号： G06F1/12 ,  G11C7/1051 ,  G11C7/1066

摘要： A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

摘要翻译： 一种用于补偿定时信号的方法，其中至少一个数据信号的数据状态的输出被同步。 该方法包括接收当前的数据状态集合和下一组数据状态，识别当前数据状态集合之间的状态转换和下一组数据状态，该组数据状态至少部分地决定了应用于定时信号的补偿量 在当前数据状态集合和下一组数据状态之间识别的状态转换上，并将确定的补偿量应用于定时信号，使得补偿适用于下一组数据状态的输出。

公开(公告)号：US09906355B2

公开(公告)日：2018-02-27

申请号：US14758973

申请日：2013-01-09

申请人： Michael Priel ,  Leonid Fleshel ,  Roman Mostinski ,  Vladimir Nusimovich

发明人： Michael Priel ,  Leonid Fleshel ,  Roman Mostinski ,  Vladimir Nusimovich

IPC分类号： H04L7/00 ,  G11C19/00 ,  G01R31/317 ,  G01R31/28

CPC分类号： H04L7/00 ,  G01R31/2837 ,  G01R31/2884 ,  G01R31/31712 ,  G11C19/00

摘要： There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.

公开(公告)号：US20150206559A1

公开(公告)日：2015-07-23

申请号：US14415153

申请日：2012-07-20

申请人： Michael Priel ,  Leonid Fleshel ,  Dan Kuzmin

发明人： Michael Priel ,  Leonid Fleshel ,  Dan Kuzmin

IPC分类号： G11C7/10 ,  G11C7/06

CPC分类号： G11C7/1072 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/22 ,  G11C19/00 ,  G11C19/28 ,  G11C29/32 ,  G11C2207/007

摘要： A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

摘要翻译： 描述了包括至少一个包括多个锁存装置的寄存器阵列的寄存器文件模块。 多个锁存装置被布置为当寄存器文件模块被配置为在第一功能操作模式下操作时，分别提供存储器位单元，并且至少一个时钟控制部件被布置成接收时钟信号并传播时钟 信号到至少一个寄存器阵列内的锁存器件。 寄存器文件模块可配置为以第二扫描模式操作，其中至少一个寄存器阵列内的锁存器件被布置成至少一个扫描链。 所述至少一个时钟控制部件布置成将所述时钟信号传播到所述至少一个寄存器阵列内的锁存器件，使得所述至少一个扫描链内的另外的锁存器件接收所述时钟信号的反相形式。

公开(公告)号：US08598949B2

公开(公告)日：2013-12-03

申请号：US13634730

申请日：2010-06-11

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： G05F1/10

CPC分类号： H03K3/00 ,  H03K3/012 ,  H03K19/0008

摘要： A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information.

摘要翻译： 一种方法和电子电路，所述方法包括：向切换电路发送状态保持电源选通（SRPG）电路和向第一电源发送指示SRPG电路应以功能模式工作的控制信号; 由开关电路将第三电网耦合到第一电网; 通过第一电网，开关电路和第三电网从第一电源向SRPG电路供电; 经由第二电网从第二电源向第二电路供电; 向SRPG电路和第一电源发送指示SRPG电路在状态保持模式下工作的控制信号; 由开关电路将第三电网耦合到第二电网; 通过第二电网，开关电路和第三电网从第二电源向SRPG电路供电; 经由所述第二电网从所述第二电源向所述第二电路供电; 并通过SRPG状态信息存储。

公开(公告)号：US20120239960A1

公开(公告)日：2012-09-20

申请号：US13510103

申请日：2009-11-30

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  G11C7/1051 ,  G11C7/1066

摘要： A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

摘要翻译： 一种用于补偿定时信号的方法，其中至少一个数据信号的数据状态的输出被同步。 该方法包括：接收当前的一组数据状态和下一组数据状态，识别当前数据状态集合与下一组数据状态之间的状态转换，至少至少确定应用于定时信号的补偿量 部分地基于在当前数据状态集合和下一组数据状态之间识别的状态转换，以及将确定的补偿量应用于定时信号，使得补偿适用于输出下一组数据状态。

公开(公告)号：US20120236630A1

公开(公告)日：2012-09-20

申请号：US13509922

申请日：2009-11-30

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： G11C11/24 ,  H01L21/02 ,  H01L27/108

CPC分类号： H01L23/5223 ,  G11C2029/5002 ,  H01L22/14 ,  H01L22/22 ,  H01L23/49589 ,  H01L23/5286 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.

摘要翻译： 用于集成电路（IC）的旁路电容器电路包括一个或多个电容性器件，每个电容器件布置在包括IC的管芯的密封环区域的段中。 提供用于IC的旁路电容的方法包括提供包括多个芯片的半导体晶片装置，每个芯片包括IC; 在所述IC中的至少一个的密封环区域中布置一个或多个电容性装置; 切割半导体晶片器件; 在测试模式中，对于所述一个或多个电容性装置中的每一个，启用所述电容性装置，确定指示所述电容性装置的可操作性的可操作性参数值，以及将所述可操作性参数存储在存储装置中; 并且在正常操作模式中，根据具有指示对应的电容性器件的非缺陷性的相关联的可操作性参数值的一个或多个电容器件的电容，向IC提供旁路电容。