摘要:
A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.
摘要:
A method and system for improving processing performance by using activity factor headroom provides improved performance while meeting power management constraints in a processing system. The method and system estimate the power consumption of the system from a model that relates measured activities at a present operating point to power consumption for any available operating point of one or more processors in the system. The method then chooses the operating point(s) with the highest performance among the available operating points that will still meet budgetary constraints or specific thresholds of power consumption. The budgetary constraints or specific thresholds may be dynamically adjusted, and the method will update the operating point(s) to maintain safe operation and maximize performance. The method provides the best performance for the executing workload while ensuring safe operation.
摘要:
A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.
摘要:
The forgoing objects are achieved as is now described. In information storage systems in which data retrieval requires movement of at least one physical element, a measurable amount of energy and time are required to reposition that physical element in response to each data write or read request. After selecting one or more data requests for dispatch based solely on an approaching or past due time deadline, additional requests are identified for data to be read or written to locations which are in close proximity to previously scheduled requests, obviating the need to expend the full amount of energy and time required to accelerate the physical element and then decelerate the physical element to position it over the desired area within the information storage system. In this manner, data may be transferred to or retrieved from an information storage system more efficiently with less expenditure of energy and time.
摘要:
A method, system, and computer program product for dynamic power and performance calibration of a data processing system are provided in the illustrative embodiments. A synthesized program loaded in the data processing system is executed responsive to detecting an event in the data processing system. The synthesized program is configured to generate a set of data that is indicative of the data processing system's power-performance characteristics under varying conditions of operation. Using the set of data, a determination is made of a performance limit on an operation of the data processing system under present operating conditions of the data processing system. A parameter of the data processing system is calibrated to operate the data processing system within the performance limit.
摘要:
A system, apparatus and method for transmitting data on a private network in blocks of data without using TCP/IP as a protocol are provided. When data is to be transmitted on a private network, the data is divided into a plurality of packets and a MAC header is added to each packet. The header contains hardware addresses of the transmitting and receiving hosts as well as parameters of the data being transmitted. The hardware addresses are used to route the packets through the private network therefore obviating the use of TCP/IP to perform the same task. The data is ordinarily stored in contiguous sectors of a storage device; thus, ensuring that almost every packet will either contain data from a block of sectors or is a receipt acknowledgement of such packet.
摘要:
A processing system and computer program provides memory power management and memory failure management in large scale systems. Upon a decision to take a memory module off-line or place the module in an increased-latency state for power management, or upon a notification that a memory module has failed or been taken off-line or has had latency increased by another power management control mechanism, a hypervisor that supports multiple virtual machines checks the use of pages by each virtual machine and its guest operating system by using a reverse mapping. The hypervisor determines which virtual machines are using a particular machine memory page and may re-map the machine memory page to another available machine page, or may notify the virtual machines that the memory page has become or is becoming unavailable via a fault or other notification mechanism. Alternatively, or in the absence of a response from a virtual machine, the hypervisor can shut down the affected partition(s).