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1.发明授权Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle 失效用于存储用于随后的页错误存储器周期中的设备行指示器的装置和方法公开(公告)号：US06199151B1
公开(公告)日：2001-03-06
申请号：US09092591
申请日：1998-06-05
IPC分类号： G06F1200
CPC分类号： G06F12/1027 , G06F12/0215 , G06F12/06
摘要： An apparatus and method for selecting a row of memory devices. A row value that indicates one of a plurality of chip select signals is stored in a storage element that is associated with a first address. A memory access request is received that includes the first address. The one of the plurality of chip select signals indicated by the row value is asserted to select one of a plurality of rows of memory devices.
摘要翻译： 一种用于选择一行存储器件的装置和方法。 指示多个芯片选择信号之一的行值被存储在与第一地址相关联的存储元件中。 接收到包含第一个地址的存储器访问请求。 由行值表示的多个片选信号之一被断言以选择多行存储器件中的一个。
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公开(公告)号：US06226730B1
公开(公告)日：2001-05-01
申请号：US09092426
申请日：1998-06-05
IPC分类号： G06F1210
CPC分类号： G06F12/0215
摘要： An apparatus and method for accessing a memory. A source address that includes a page address and a page offset is received. The page address requires translation in order to form a first address that can be used to transfer data from a row of memory cells into a sense amplifier array in a memory. The page address is compared to contents of one or more page registers to determine if the data is present in the sense amplifier array as a result of a previous memory access. A second address is asserted to access a portion of the data if the data is determined to be present in the sense amplifier array.
摘要翻译： 一种用于访问存储器的装置和方法。 接收包含页面地址和页面偏移的源地址。 页面地址需要转换以形成可以用于将数据从一行存储器单元传送到存储器中的读出放大器阵列的第一地址。 将页面地址与一个或多个页面寄存器的内容进行比较，以确定数据是否作为先前存储器访问的结果存在于读出放大器阵列中。 如果数据被确定为存在于读出放大器阵列中，则第二地址被断言以访问数据的一部分。
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公开(公告)号：US5860128A
公开(公告)日：1999-01-12
申请号：US724370
申请日：1996-10-01
CPC分类号： G11C7/106 , G11C29/50 , G11C7/1024 , G11C7/1051 , G11C7/1078 , G11C8/18 , G11C11/401
摘要： A novel method for performing memory accesses. Falling edges of a column address strobe (CAS) signal are used to cause dynamic random access memories (DRAMs) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches. A memory latch data (MLAD) signal is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal. Since the same signal (CAS) is used to control when the data is driven by the DRAMs and when the data is latched by the latches, the differences in output timings, signal path delays, and loads are avoided. The use of expensive timing compensation circuits and special tuning of these circuits for each circuit board redesign is thereby avoided.
摘要翻译： 一种用于执行存储器访问的新方法。 列地址选通（CAS）信号的下降沿用于使动态随机存取存储器（DRAM）将与当前地址相对应的数据驱动到耦合到一组锁存器的输入的数据总线上。 存储器锁存数据（MLAD）信号用于使能该组锁存器。 当MLAD信号被置位时，锁存器响应于CAS信号的下降沿在输入端锁存数据。 当MLAD信号无效时，锁存器不会响应CAS信号的下降沿在输入端锁存数据。 由于使用相同的信号（CAS）来控制数据由DRAM驱动，并且当数据被锁存器锁存时，避免了输出定时，信号路径延迟和负载的差异。 因此避免了使用昂贵的定时补偿电路和对每个电路板进行重新设计的这些电路的特殊调谐。
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4.发明授权Configurable page closing method and apparatus for multi-port host bridges 失效用于多端口主机桥的可配置的页面关闭方法和装置公开(公告)号：US06370624B1
公开(公告)日：2002-04-09
申请号：US09712010
申请日：2000-11-13
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译： 一种用于多端口主机桥的页面关闭方法和装置。 根据所公开的方法，从多个命令端口接收多个存储器访问命令。 从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。 响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。 关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。
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5.发明授权Configurable page closing method and apparatus for multi-port host bridges 失效用于多端口主机桥的可配置的页面关闭方法和装置公开(公告)号：US06199145B1
公开(公告)日：2001-03-06
申请号：US09032434
申请日：1998-02-27
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译： 一种用于多端口主机桥的页面关闭方法和装置。 根据所公开的方法，从多个命令端口接收多个存储器访问命令。 从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。 响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。 关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。
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6.发明授权Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations 失效用于寻址包括具有多种配置的存储器设备的存储器资源的方法和装置
公开(公告)号：US6154825A
公开(公告)日：2000-11-28
申请号：US814733
申请日：1997-03-07
CPC分类号： G06F12/06 , G06F12/0215
摘要： A method and apparatus for accessing a memory resource, such as an array of DRAM modules, is described. The methodology commences with the receipt of a memory address during a memory access cycle. A row address is then generated by selecting predetermined bits of the memory address as the row address. Concurrently with the generation of the row address, a determination is made as to the configuration of a memory device within the memory resource and targeted by the memory address. Thereafter, a column address is generated by selecting bits of the memory address as the column address based on the configuration of the targeted memory device. The time required for the determination of the configuration of the targeted memory device is thus absorbed within the time expended generating the row address.
摘要翻译： 描述了用于访问诸如DRAM模块阵列之类的存储器资源的方法和装置。 该方法开始于在存储器访问周期期间接收到存储器地址。 然后通过选择存储器地址的预定位作为行地址来生成行地址。 与行地址的产生同时，确定存储器资源内的存储器设备的配置并且由存储器地址对准。 此后，基于目标存储器件的配置，通过选择存储器地址的位作为列地址来生成列地址。 因此，确定目标存储器件的配置所需的时间在生成行地址的时间内被吸收。
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公开(公告)号：US20150032941A1
公开(公告)日：2015-01-29
申请号：US14128669
申请日：2013-07-25
申请人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
发明人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F12/02 , G06F13/12 , G06F13/16 , G06F13/1668 , G06F13/38 , G06F13/4234 , G06F2212/7202
摘要： In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.
摘要翻译： 在一个实施例中，存储器接口可以发送请求被发送的指示。 该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。 存储器接口可以经由总线将请求发送到非易失性存储器。 请求可以包括可用于标识用于存储或读取数据的位置的地址。 非易失性存储器可以从总线获取请求并处理请求。 在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。 存储器接口可以向总线授予对非易失性存储器的访问。 在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。
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8.发明授权System and method for controlling power states of a memory device via detection of a chip select signal 有权用于通过芯片选择信号的检测来控制存储器件的电源状态的系统和方法公开(公告)号：US06618791B1
公开(公告)日：2003-09-09
申请号：US09677138
申请日：2000-09-29
申请人： James M. Dodd , Michael W. Williams
发明人： James M. Dodd , Michael W. Williams
IPC分类号： G06F1200
CPC分类号： G11C5/143 , G06F1/3225 , G06F1/3275 , Y02D10/14 , Y02D50/20
摘要： A memory system and a method for controlling power states of a memory device, or a portion thereof, are provided. The memory system includes memory devices, such as DRAMs, a memory controller, chip select lines, and logic for detecting chip select signals from the chip select lines. Each memory device, or a portion therein, is connected to the memory controller by a chip select line. Each chip select line allows the transmission of a chip select signal to a corresponding memory device, or a corresponding portion of the memory device, to select the corresponding memory device, or a portion thereof, to receive commands. Logic is provided to detect the chip select signal. When the logic detects a chip select signal provided to a corresponding memory device, or a portion thereof, that is in a power state lower than its idle state, the memory device, or a portion thereof, is automatically moved from the lower power state to a higher power state.
摘要翻译： 提供了一种用于控制存储器件或其一部分的电源状态的存储器系统和方法。 存储器系统包括诸如DRAM的存储器件，存储器控制器，芯片选择线以及用于检测来自芯片选择线的芯片选择信号的逻辑。 每个存储器件或其中的部分通过芯片选择线连接到存储器控制器。 每个芯片选择线允许将芯片选择信号传输到对应的存储器件或存储器件的相应部分，以选择相应的存储器件或其一部分来接收命令。 提供逻辑来检测芯片选择信号。 当逻辑检测到提供给处于低于其空闲状态的功率状态的相应存储器件或其一部分的芯片选择信号时，存储器件或其一部分自动从较低功率状态移动到 更高的功率状态。
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9.发明授权Circuit, system and method for executing a refresh in an active memory bank 有权用于在活动存储体中执行刷新的电路，系统和方法公开(公告)号：US06400631B1
公开(公告)日：2002-06-04
申请号：US09662728
申请日：2000-09-15
申请人： Michael W. Williams , Jim M. Dodd
发明人： Michael W. Williams , Jim M. Dodd
IPC分类号： G11C1304
CPC分类号： G11C11/406
摘要： A memory containing a plurality of memory banks and a plurality of sense amplifiers. Also, the memory device contains a multiplexer and logic. The logic receives a refresh request for one of the plurality of memory banks and instructs the multiplexer to select one of the plurality of sense amplifiers in response to the refresh request.
摘要翻译： 一种包含多个存储体和多个读出放大器的存储器。 此外，存储器件包含多路复用器和逻辑。 逻辑接收对多个存储器组中的一个的刷新请求，并且指示多路复用器响应于刷新请求选择多个读出放大器之一。
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公开(公告)号：US20090316800A1
公开(公告)日：2009-12-24
申请号：US12583920
申请日：2009-08-24
CPC分类号： G06F13/28 , G11C5/066 , G11C7/10 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C11/4076 , G11C11/4096
摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
摘要翻译： 实施例通过高速串行链路以比高速串行链路常规操作更慢的速度提供对存储器的访问。 实施例可以包括具有耦合到协议识别电路的差分接收器的存储器设备，具有与差分接收器的第一输入端耦合的第一接收器的低速接收电路和与差分接收器的第二输入端耦合的第二接收器 其中低速接收电路与协议识别电路耦合，允许第一和第二接收机以与差分接收机不同的频率访问协议识别块。
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