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公开(公告)号：US20190324523A1
公开(公告)日：2019-10-24
申请号：US16457930
申请日：2019-06-29
IPC分类号： G06F1/3234 , G06F1/3225 , G06F3/06
摘要： A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.
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公开(公告)号：US20220261308A1
公开(公告)日：2022-08-18
申请号：US17733627
申请日：2022-04-29
申请人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Swadesh Choudhary , Zuoguo Wu , Gerald Pasdast
发明人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Swadesh Choudhary , Zuoguo Wu , Gerald Pasdast
摘要： Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.
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公开(公告)号：US20220342841A1
公开(公告)日：2022-10-27
申请号：US17856050
申请日：2022-07-01
申请人： Swadesh Choudhary , Debendra Das Sharma , Narasimha Lanka , Lakshmipriya Seshan , Gerald Pasdast , Zuoguo Wu
发明人： Swadesh Choudhary , Debendra Das Sharma , Narasimha Lanka , Lakshmipriya Seshan , Gerald Pasdast , Zuoguo Wu
摘要： A die-to-die (D2D) adapter couples to a protocol layer block using a first interface to couple to a protocol layer block and couples to a physical layer (PHY) block using a second interface. The D2D adapter is to determine parameters of a D2D link to couple a first die to a second die and select, based on the parameters, a particular one of a plurality of different data formats for use on the D2D link. Protocol layer data is received at the D2D adapter over the first interface from the protocol layer block. The D2D adapter passes the protocol layer data over the second interface to the PHY block based on the particular data format.
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公开(公告)号：US20220271912A1
公开(公告)日：2022-08-25
申请号：US17743085
申请日：2022-05-12
申请人： Gerald Pasdast , Peipei Wang , Lakshmipriya Seshan , Juan Zeng , Zuoguo Wu , Zhiguo Qian , Narasimha Lanka , Debendra Das Sharma , Swadesh Choudhary
发明人： Gerald Pasdast , Peipei Wang , Lakshmipriya Seshan , Juan Zeng , Zuoguo Wu , Zhiguo Qian , Narasimha Lanka , Debendra Das Sharma , Swadesh Choudhary
IPC分类号： H04L7/00
摘要： Embodiments herein may relate to a die for use in a multi-die package. The die may include clock circuitry that is able to identify a phase of a data signal to be transmitted and a phase of a clock signal to be transmitted on a die-to-die (D2D) link. The clock circuitry may further be configured adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal such that the clock signal and the data signal are received by a receiver die of the D2D link with a 90 degree phase difference. Other embodiments may be described and claimed.
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5.发明授权公开(公告)号：US07228362B2
公开(公告)日：2007-06-05
申请号：US10815899
申请日：2004-03-31
CPC分类号： G06F13/1626
摘要： Various embodiments of the invention relate to an apparatus and method for efficiently implementing out-of-order servicing of read requests originating from an input/output (I/O) interface with minimal additional storage. For example, a number of read entries may be generated from data read requests stored in a first-in-first-out in a first order. The read entries are stored in a storage device and each read entry identifies internal data reads to read data to service the data read request to which the read entry corresponds. A controller coupled to the storage structure may then submit the internal data reads a central arbiter to read data in a second order that is different than the first order. Moreover, the controller also allows the second order to include internal data reads from one read entry, before a completing servicing of another partially serviced read entry, thus providing “simultaneous” servicing of several read entries.
摘要翻译： 本发明的各种实施例涉及一种用于以最小额外存储有效地实现源自输入/输出（I / O）接口的读取请求的无序服务的装置和方法。 例如，可以从以第一顺序先进先出存储的数据读取请求生成多个读入条目。 读取的条目存储在存储设备中，并且每个读取条目标识内部数据读取以读取数据以服务读取条目对应的数据读取请求。 耦合到存储结构的控制器然后可以提交内部数据读取中央仲裁器，以与第一顺序不同的第二顺序读取数据。 此外，控制器还允许在对另一部分服务读取条目进行完成服务之前，第二顺序包括来自一个读取条目的内部数据读取，从而为多个读取条目提供“同时”服务。
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公开(公告)号：US20220334932A1
公开(公告)日：2022-10-20
申请号：US17855720
申请日：2022-06-30
申请人： Debendra Das Sharma , Swadesh Choudhary , Sridhar Muthrasanallur , Narasimha Lanka , Zuoguo Wu , Gerald Pasdast , Lakshmipriya Seshan
发明人： Debendra Das Sharma , Swadesh Choudhary , Sridhar Muthrasanallur , Narasimha Lanka , Zuoguo Wu , Gerald Pasdast , Lakshmipriya Seshan
摘要： A retimer includes a first port to couple to a die over a first interconnect, where the first interconnect includes a defined set of lanes and utilizes a first communication technology, and the die is located on a first package with the retimer. The retimer further includes a second port to couple to another retimer over a second interconnect, where the second interconnect utilizes a different second communication technology, and the second retimer is located on a different, second package to facilitate a longer reach communication channel.
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公开(公告)号：US20220262756A1
公开(公告)日：2022-08-18
申请号：US17733545
申请日：2022-04-29
申请人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Gerald Pasdast , Zuoguo Wu , Swadesh Choudhary
发明人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Gerald Pasdast , Zuoguo Wu , Swadesh Choudhary
IPC分类号： H01L23/00 , H01L25/10 , G06F1/04 , H01L23/12 , H01L23/538
摘要： Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.
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公开(公告)号：US20220237138A1
公开(公告)日：2022-07-28
申请号：US17708386
申请日：2022-03-30
申请人： Narasimha Lanka , Lakshmipriya Seshan , Swadesh Choudhary , Debendra Das Sharma , Zuoguo Wu , Gerald Pasdast
发明人： Narasimha Lanka , Lakshmipriya Seshan , Swadesh Choudhary , Debendra Das Sharma , Zuoguo Wu , Gerald Pasdast
摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.
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公开(公告)号：US20220222198A1
公开(公告)日：2022-07-14
申请号：US17708367
申请日：2022-03-30
申请人： Narasimha Lanka , Swadesh Choudhary , Debendra Das Sharma , Lakshmipriya Seshan , Zuoguo Wu , Gerald Pasdast
发明人： Narasimha Lanka , Swadesh Choudhary , Debendra Das Sharma , Lakshmipriya Seshan , Zuoguo Wu , Gerald Pasdast
IPC分类号： G06F13/42 , H01L25/065 , H01L23/538 , G06F13/40
摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.
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公开(公告)号：US20220012140A1
公开(公告)日：2022-01-13
申请号：US17485180
申请日：2021-09-24
摘要： A device includes a port with a replay buffer and protocol logic to receive a flit in a sequence of flits to be sent on a point-to-point link and determine an error in the flit. Based on the error, a copy of the flit is stored in a first position within the replay buffer as well as a copy of a next flit received in the sequence of flits, which is stored in a second position within the replay buffer. The copies of the flits are then written to a register for access by software.
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