公开(公告)号：US06884666B2

公开(公告)日：2005-04-26

申请号：US10624074

申请日：2003-07-21

申请人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

发明人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

IPC分类号： G02F1/136 ,  G02F1/1345 ,  G02F1/1368 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/768 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/522 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78645

摘要： A current path pattern of semiconductor material is formed on the insulating principal surface of a substrate. A gate pattern three-dimensionally crosses the current path pattern in first and second cross areas. A channel region of the current path pattern is defined in an area superposed upon by the gate pattern. A gate insulating film is disposed between the current path pattern and gate pattern. The current path pattern has a lightly doped drain structure on both sides of the channel region in the first cross area, and is not provided with the lightly doped drain structure in regions in contact with the channel region in the second cross area. TFTs are provided having a small off-current and being not necessary for high precision position alignment during manufacture processes even if a gate length is short.

摘要翻译： 半导体材料的电流路径图案形成在基板的绝缘主表面上。 栅极图案在第一和第二交叉区域中三维地穿过当前路径图案。 当前路径图案的通道区域被限定在由栅极图案叠加的区域中。 栅极绝缘膜设置在电流路径图案和栅极图案之间。 电流路径图案在第一交叉区域中的沟道区域的两侧上具有轻掺杂的漏极结构，并且在与第二十字区域中的沟道区域接触的区域中不设置轻掺杂漏极结构。 提供具有小的截止电流的TFT，并且即使栅极长度短，也不需要在制造过程中的高精度位置对准。

公开(公告)号：US06628349B1

公开(公告)日：2003-09-30

申请号：US09651876

申请日：2000-08-30

申请人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

发明人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

IPC分类号： G02F1136

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78645

摘要： A liquid crystal display substrate including gate and drain bus lines that are electrically insulated from each other at cross areas, pixel electrodes between the cross areas, and first thin film transistors connecting corresponding drain bus lines and pixel electrodes. Each first thin film transistor includes a channel region where current flows in a first direction, and first and second impurity doped regions of, respectively, first and second impurity concentrations. The first and second doped regions sandwich the channel region. The second impurity concentration is higher than the first. Also, a second thin film transistor is formed in the peripheral circuit area, and includes a channel region where current flows in a second direction that is perpendicular to the first direction. Third impurity doped regions, disposed on both sides of the channel region, have a third impurity concentration.

摘要翻译： 一种液晶显示基板，包括在交叉区域彼此电绝缘的栅极和漏极总线，以及交叉区域之间的像素电极和连接相应的漏极总线和像素电极的第一薄膜晶体管。 每个第一薄膜晶体管包括电流沿第一方向流动的沟道区，以及分别为第一和第二杂质浓度的第一和第二杂质掺杂区。 第一和第二掺杂区夹着沟道区。 第二杂质浓度高于第一杂质浓度。 此外，第二薄膜晶体管形成在外围电路区域中，并且包括电流沿与第一方向垂直的第二方向流动的沟道区域。 设置在沟道区两侧的第三杂质掺杂区具有第三杂质浓度。

公开(公告)号：US4914080A

公开(公告)日：1990-04-03

申请号：US300889

申请日：1989-01-24

申请人： Kohta Yoshikawa ,  Naoki Awaji ,  Kyung-ho Park ,  Nagisa Ohsako ,  Seigen Ri

发明人： Kohta Yoshikawa ,  Naoki Awaji ,  Kyung-ho Park ,  Nagisa Ohsako ,  Seigen Ri

IPC分类号： H01L39/24

CPC分类号： H01L39/2432 ,  Y10S505/73 ,  Y10S505/732

摘要： A method for fabricating a superconductive film composed of a RE.sub.1 Ba.sub.2 Cu.sub.3 O.sub.x compound, or a (Bi.Sr.Ca.Cu.O) compound. In a first embodiment, oxides or carbonates of the component materials, namely Y.sub.2 O.sub.3, BaCO.sub.3, and CuO are mixed in atomic ratios of 1:2:3, according to the chemical formula of RE.sub.1 Ba.sub.2 Cu.sub.3 O.sub.x, and sintered to create a rhombic perovskite structure. The sintered mixture is powdered again, with added powdered amounts of Y.sub.2 O.sub.3 and powdered metallic Cu, and sintered. The sintered product is used as the source for an electron beam evaporator. In a second embodiment the (Bi.Sr.Ca.Cu.O) compound is formed into a sintered pellet which is composed of a mixture of one part of BiO, 3-15 parts of SrCO.sub.3, 4-30 parts of CaCO.sub.3, and 2-5 parts of CuO, in atomic ratios of Bi, Sr, Ca and Cu.

公开(公告)号：US06912019B2

公开(公告)日：2005-06-28

申请号：US10315628

申请日：2002-12-10

申请人： Kohta Yoshikawa

发明人： Kohta Yoshikawa

IPC分类号： G02F1/136 ,  G02F1/1345 ,  G02F1/1368 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/768 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/522 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78645

摘要： A method of making a semiconductor device, including the steps of forming, upon a substrate, a semiconductor film, an insulating film, and a conductive film. Part of the upper surface of the conductive film is covered with a resist pattern so that the semiconductor film protrudes from the edges of the resist pattern. Then, the conductive film is etched using the resist pattern as a mask to leave a patterned conductive film, whereby side wall additives of reaction byproducts are generated. Next, the insulating film is etched using the patterned conductive film and side wall additives as a mask, and the side wall additives are removed. Then, impurities are implanted in the semiconductor film using the patterned conductive film as a mask so that impurities transmit through the insulating film, which expose on both sides of the patterned conductive film after removing the side wall additives. Finally, the resist pattern is removed.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成半导体膜，绝缘膜和导电膜的步骤。 导电膜的上表面的一部分被抗蚀剂图案覆盖，使得半导体膜从抗蚀剂图案的边缘突出。 然后，使用抗蚀剂图案作为掩模蚀刻导电膜以留下图案化导电膜，由此产生反应副产物的侧壁添加剂。 接下来，使用图案化导电膜和侧壁添加剂作为掩模来蚀刻绝缘膜，并且去除侧壁添加剂。 然后，使用图案化导电膜作为掩模将杂质注入到半导体膜中，使得杂质透过绝缘膜，除去侧壁添加剂后，在图案化导电膜的两侧露出。 最后，去除抗蚀剂图案。