Multi-Current Harmonized Paths for Low Power Local Interconnect Network (LIN) Receiver
    1.
    发明申请
    Multi-Current Harmonized Paths for Low Power Local Interconnect Network (LIN) Receiver 有权
    低功耗局域互联网络(LIN)接收机的多电流协调路径

    公开(公告)号:US20140269996A1

    公开(公告)日:2014-09-18

    申请号:US13842386

    申请日:2013-03-15

    Abstract: A LIN receiver includes a single, low power structure for both sleep and silent modes, with a single comparator for detecting LIN signaling during both sleep and silent modes as well as during active mode. In some embodiments, full receiving capability is implemented with a current as low as 5 microamps. In particular, dominant and recessive levels for the wakeup bloc are identical to those of standard LIN levels, fixed at about 3.5 V. Consequently, full LIN receiving capability is available during sleep mode.

    Abstract translation: LIN接收机包括用于睡眠和静音模式的单个低功率结构,单个比较器用于在睡眠和静音模式以及活动模式期间检测LIN信号。 在一些实施例中,以低至5微安的电流实现完全接收能力。 特别地,唤醒块的主要和隐性级别与标准LIN级别相同,固定在约3.5V。因此,在睡眠模式期间可以获得完整的LIN接收能力。

    Main Clock High Precision Oscillator
    5.
    发明申请
    Main Clock High Precision Oscillator 有权
    主时钟高精度振荡器

    公开(公告)号:US20150146832A1

    公开(公告)日:2015-05-28

    申请号:US14554570

    申请日:2014-11-26

    Abstract: A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.

    Abstract translation: 时钟振荡器包括产生高速时钟信号并包括数字微调功能的高速振荡器; 在时钟输入端接收所述高速时钟信号的计数器; 具有低漂移和控制所述计数器的时基,其中所述计数器产生参考值和计数器值之间的差; 以及接收所述差分值并提供所述高速振荡器的修整数据的数字积分器。

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