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    Methods For Controllable Metal And Barrier-Liner Recess
    1.
    发明申请
    Methods For Controllable Metal And Barrier-Liner Recess 有权

    公开(公告)号：US20210305091A1

    公开(公告)日：2021-09-30

    申请号：US17345683

    申请日：2021-06-11

    申请人： Micromaterials LLC

    发明人： He Ren ,  Amrita B. Mullick ,  Regina Freed ,  Mehul Naik ,  Uday Mitra

    IPC分类号： H01L21/768

    摘要： Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

    Fully self-aligned via
    4.
    发明授权
    Fully self-aligned via 有权

    公开(公告)号：US10522404B2

    公开(公告)日：2019-12-31

    申请号：US16520546

    申请日：2019-07-24

    申请人： Micromaterials LLC

    发明人： Ying Zhang ,  Abhijit Basu Mallick ,  Regina Freed ,  Nitin K. Ingle ,  Uday Mitra ,  Ho-yung Hwang

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532

    摘要： A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.

    Methods of producing self-aligned grown via
    8.
    发明授权
    Methods of producing self-aligned grown via 有权

    公开(公告)号：US10573555B2

    公开(公告)日：2020-02-25

    申请号：US16116421

    申请日：2018-08-29

    申请人： Micromaterials LLC

    发明人： Ying Zhang ,  Regina Freed ,  Nitin K. Ingle ,  Ho-yung Hwang ,  Uday Mitra ,  Abhijit Basu Mallick

    IPC分类号： H01L21/768 ,  H01L21/311 ,  H01J37/32 ,  H01L23/532 ,  H01L21/02 ,  H01L21/3105 ,  H01L23/522

    摘要： Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed portions of the first conductive lines and pillars are formed from the first metal film. A second insulating layer is deposited around the pillars. The pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.

    Methods of producing fully self-aligned vias and contacts
    9.
    发明授权
    Methods of producing fully self-aligned vias and contacts 有权

    公开(公告)号：US10553485B2

    公开(公告)日：2020-02-04

    申请号：US16015714

    申请日：2018-06-22

    申请人： Micromaterials LLC

    发明人： Ying Zhang ,  Regina Freed ,  Nitin K. Ingle ,  Ho-yung Hwang ,  Uday Mitra ,  Abhijit Basu Mallick ,  Sanjay Natarajan

    IPC分类号： H01L21/768 ,  H01L21/67 ,  H01L21/3213

    摘要： Methods and apparatus to form fully self-aligned vias are described. First conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed first conductive lines and pillars are formed from the first metal film. Some of the pillars are selectively removed and a second insulating layer is deposited around the remaining pillar. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.

    Fully self-aligned via
    10.
    发明授权
    Fully self-aligned via 有权

    公开(公告)号：US10424507B2

    公开(公告)日：2019-09-24

    申请号：US15679458

    申请日：2017-08-17

    申请人： Micromaterials LLC

    发明人： Ying Zhang ,  Abhijit Basu Mallick ,  Regina Freed ,  Nitin K. Ingle ,  Uday Mitra ,  Ho-yung Hwang

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532

    摘要： A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.