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    Power module package baseplate with step recess design
    1.
    发明授权
    Power module package baseplate with step recess design 有权

    公开(公告)号：US12131981B2

    公开(公告)日：2024-10-29

    申请号：US18357931

    申请日：2023-07-24

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Yushuang Yao ,  Vemmond Jeng Hung Ng

    IPC分类号： H01L23/492 ,  H01L21/48

    CPC分类号： H01L23/4924 ,  H01L21/4871

    摘要： Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.

    Semiconductor device and method for manufacturing semiconductor device
    3.
    发明授权
    Semiconductor device and method for manufacturing semiconductor device 有权

    公开(公告)号：US12057375B2

    公开(公告)日：2024-08-06

    申请号：US18324479

    申请日：2023-05-26

    申请人： ROHM CO., LTD.

    发明人： Maiko Hatano

    IPC分类号： H01L23/492 ,  H01L23/00 ,  H01L23/31

    CPC分类号： H01L23/4924 ,  H01L23/3114 ,  H01L24/83 ,  H01L2224/8384

    摘要： A semiconductor device A1 includes a semiconductor element 10A having an element obverse face 101 and an element reverse face 102, the element obverse face 101 having an obverse face electrode 11 formed thereon and the element reverse face 102 having a reverse face electrode 12 formed thereon, a conductive substrate 22A including an obverse face 221A opposed to the element reverse face 102, and to which the reverse face electrode 12 is conductively bonded, a conductive substrate 22B including an obverse face 221B and spaced from the conductive substrate 22A in a width direction x, and a lead member 51 extending in the width direction x, and electrically connecting the obverse face electrode 11 and the conductive substrate 22B. The lead member 51 is located ahead of the obverse face 221B in the direction in which the obverse face 221B is oriented, and bonded to the obverse face electrode 11 via a lead bonding layer 32. The conductive substrate 22A, the semiconductor element 10A, and the lead bonding layer 32 overlap with the conductive substrate 22B, as viewed in the width direction x.

    Power module package baseplate with step recess design
    7.
    发明授权
    Power module package baseplate with step recess design 有权

    公开(公告)号：US11735504B2

    公开(公告)日：2023-08-22

    申请号：US16949869

    申请日：2020-11-18

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Yushuang Yao ,  Vemmond Jeng Hung Ng

    IPC分类号： H01L23/492 ,  H01L21/48

    CPC分类号： H01L23/4924 ,  H01L21/4871

    摘要： Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.

    SYSTEM IN PACKAGE WITH FLIP CHIP DIE OVER MULTI-LAYER HEATSINK STANCHION
    9.
    发明公开
    SYSTEM IN PACKAGE WITH FLIP CHIP DIE OVER MULTI-LAYER HEATSINK STANCHION 审中-公开

    公开(公告)号：US20230170275A1

    公开(公告)日：2023-06-01

    申请号：US17538583

    申请日：2021-11-30

    申请人： Qorvo US, Inc.

    发明人： Kelly M. Lear ,  Jeffrey Miller ,  Mihir Roy ,  Christine Blair

    IPC分类号： H01L23/367 ,  H01L23/492 ,  H01L23/48

    CPC分类号： H01L23/3677 ,  H01L23/481 ,  H01L23/4924

    摘要： The present disclosure relates to a system in package having a chiplet with a first substrate and a first die deposed over the first substrate, a second die, a second substrate that the chiplet and the second die are deposed over, and a heatsink spreader deposed over the chiplet and the second die. Herein, the first substrate includes layered-cake shaped heatsink stanchions that are coupled to the first die, and the second substrate includes layered-cake shaped heatsink stanchions that are coupled to the chiplet and the second die. As such, heat generated by the first die can be dissipated by the heatsink stanchions within the first and second substrates, and heat generated by the second die can be dissipated by the heatsink stanchions within the second substrate. Furthermore, the heat generated by the first die and the second die can be dissipated by the heatsink spreader above them.