公开(公告)号：US20230034157A1

公开(公告)日：2023-02-02

申请号：US17389864

申请日：2021-07-30

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Davide Resnati ,  Gianpietro Carnevale ,  Shyam Surthi

IPC: H01L27/11582

Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11244954B2

公开(公告)日：2022-02-08

申请号：US16548320

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

公开(公告)号：US20240268116A1

公开(公告)日：2024-08-08

申请号：US18403266

申请日：2024-01-03

Applicant: Micron Technology, Inc.

Inventor： Amiya Banerjee ,  Kranthi Kumar Vaidyula ,  Davide Resnati ,  Byeung Chul Kim ,  Kyubong Jung ,  Jameer Babasaheb Mulani ,  Jae Kyu Choi ,  Gianpietro Carnevale

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. Channel openings are formed through the first and second tiers. Charge-storage material is formed in the channel openings through the first and second tiers. The charge-storage material comprises a first charge-trap density. The first charge-trap density of the charge-storage material that is in the first tiers is increased as compared to the charge-storage material that is in the second tiers to a second charge-trap density. Channel material is formed in the channel openings through the first and second tiers and that is laterally-inward of the charge-storage material. Other embodiment, including structure, are disclosed.

公开(公告)号：US20220123018A1

公开(公告)日：2022-04-21

申请号：US17561564

申请日：2021-12-23

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

公开(公告)号：US20210343736A1

公开(公告)日：2021-11-04

申请号：US16862150

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Chris M. Carlson ,  Richard J. Hill ,  Davide Resnati

IPC: H01L27/11556 ,  H01L27/06 ,  H01L27/11582 ,  G11C5/02

Abstract: An electronic structure comprising stacks comprising alternating dielectric materials and conductive materials in a cell region of the electronic structure. A pillar high-k dielectric material is adjacent to the stacks and in a pillar region of the electronic structure. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material in the pillar region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials in the cell region of the electronic structure. The cell high-k dielectric material adjoins a portion of the pillar high-k dielectric material. Additional electronic structures are disclosed, as are related electronic devices, systems, and methods of forming an electronic device.

公开(公告)号：US20210057437A1

公开(公告)日：2021-02-25

申请号：US16548320

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

公开(公告)号：US20240381646A1

公开(公告)日：2024-11-14

申请号：US18781329

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Davide Resnati ,  Gianpietro Carnevale ,  Shyam Surthi

IPC: H10B43/27

Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12082416B2

公开(公告)日：2024-09-03

申请号：US17389864

申请日：2021-07-30

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Davide Resnati ,  Gianpietro Carnevale ,  Shyam Surthi

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.