公开(公告)号：US20230395545A1

公开(公告)日：2023-12-07

申请号：US17830224

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Bret K. Street ,  Debjit Datta ,  Eiichi Nakano

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0652 ,  H01L24/80 ,  H01L24/95 ,  H01L2224/80047 ,  H01L2224/8001 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2224/08148 ,  H01L2224/95093 ,  H01L2224/80204 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/182 ,  H01L2924/1011

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

公开(公告)号：US12278202B2

公开(公告)日：2025-04-15

申请号：US17830224

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Bret K. Street ,  Debjit Datta ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/00

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

公开(公告)号：US20240282731A1

公开(公告)日：2024-08-22

申请号：US18406068

申请日：2024-01-05

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Wei Zhou ,  Debjit Datta ,  Chaiyanan Kulchaisit ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L24/08 ,  H01L21/56 ,  H01L23/295 ,  H01L24/05 ,  H01L24/13 ,  H01L24/80 ,  H01L2224/02379 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device assembly, including a semiconductor die having a frontside surface, a first plurality of bond pads at the frontside surface and a first dielectric layer at the frontside surface; and an interface die having a frontside surface and a backside surface, the interface die including a second plurality of bond pads and a second dielectric layer disposed on the backside surface of the interface die, a third dielectric layer disposed on the frontside surface of the interface die, wherein the third dielectric layer includes a mechanically altered surface opposite the frontside surface of the interface die, and a redistribution layer disposed on the third dielectric layer and above the frontside surface of the interface die, wherein hybrid bonds are disposed between the frontside surface of the semiconductor die and the backside surface of the interface die.