公开(公告)号：US20190088527A1

公开(公告)日：2019-03-21

申请号：US16193679

申请日：2018-11-16

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/683 ,  H01L21/67 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/6835 ,  H01L21/67092 ,  H01L21/67144 ,  H01L24/75 ,  H01L24/80 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68313 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/08145 ,  H01L2224/7501 ,  H01L2224/753 ,  H01L2224/7565 ,  H01L2224/75755 ,  H01L2224/75804 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/8001 ,  H01L2224/80896 ,  H01L2224/9511 ,  H01L2224/95136 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2224/80001

Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both top side processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that top sides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.

公开(公告)号：US09859246B2

公开(公告)日：2018-01-02

申请号：US14917318

申请日：2014-12-18

Applicant: EV GROUP E. THALLNER GMBH

Inventor： Andreas Fehkuhrer

IPC: H01L21/00 ,  H01L23/00 ,  B32B37/00 ,  H01L21/18 ,  H01L21/304 ,  H01L21/67 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/544 ,  B32B38/18

CPC classification number: H01L24/80 ,  B32B37/0046 ,  B32B38/1841 ,  B32B38/1858 ,  B32B2309/105 ,  B32B2457/14 ,  H01L21/187 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/08 ,  H01L24/74 ,  H01L24/75 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/0224 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/75251 ,  H01L2224/75272 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75724 ,  H01L2224/75725 ,  H01L2224/75734 ,  H01L2224/75735 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/80 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/8002 ,  H01L2224/80047 ,  H01L2224/80051 ,  H01L2224/80093 ,  H01L2224/80099 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80209 ,  H01L2224/80213 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2221/68304

Abstract: A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

公开(公告)号：US20170221856A1

公开(公告)日：2017-08-03

申请号：US15519542

申请日：2015-10-19

Applicant: BONDTECH CO., LTD.

Inventor： Akira YAMAUCHI

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L24/83 ,  B23K20/023 ,  B23K20/233 ,  B23K20/24 ,  B23K37/0408 ,  B23K37/047 ,  B23K2101/40 ,  B23K2103/50 ,  H01L21/187 ,  H01L21/67092 ,  H01L21/67259 ,  H01L21/68 ,  H01L21/6831 ,  H01L21/6838 ,  H01L21/68735 ,  H01L23/544 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/7501 ,  H01L2224/75102 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75272 ,  H01L2224/75303 ,  H01L2224/75305 ,  H01L2224/757 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75724 ,  H01L2224/75725 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/759 ,  H01L2224/75901 ,  H01L2224/7592 ,  H01L2224/75981 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/8003 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80203 ,  H01L2224/80213 ,  H01L2224/80893 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80908 ,  H01L2224/80986 ,  H01L2224/83009 ,  H01L2224/8309 ,  H01L2224/83896 ,  H01L2224/83908 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2224/8001 ,  H01L2224/80009 ,  H01L2224/80121

Abstract: A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain. A method for bonding a first substrate and a second substrate includes a step of performing hydrophilization treatment to cause water or an OH containing substance to adhere to bonding surface of the first substrate and the bonding surface of the second substrate, a step of disposing the first substrate and the second substrate with the respective bonding surfaces facing each other, and bowing the first substrate in such a way that a central portion of the bonding surface protrudes toward the second substrate side relative to an outer circumferential portion of the bonding surface, a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate at the respective central portions, and a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate across the entirety of the bonding surfaces, decreasing a distance between the outer circumferential portion of the first substrate and an outer circumferential portion of the second substrate with the respective central portions abutting each other at a pressure that maintains a non-bonded condition.

公开(公告)号：US20150048523A1

公开(公告)日：2015-02-19

申请号：US14397038

申请日：2013-04-24

Applicant: Tadatomo SUGA ,  BONDTECH CO., LTD.

Inventor： Tadatomo Suga ,  Akira Yamauchi

IPC: H01L25/065 ,  B23K31/02 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  B23K37/04 ,  B23K37/00

CPC classification number: H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2101/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.[Solution] A method for bonding plural chips each having a chip-side-bond-surface having metal regions to a substrate having plural bond portions has the step (S1) of subjecting the metal regions of the chip-side-bond-surface to surface activating treatment and hydrophilizing treatment; the step (S2) of subjecting the bond portions of the substrate to surface activating treatment and hydrophilizing treatment; the step (S3) of fitting the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portions of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal regions of the chips into contact with the bond portions of the substrate; and the step (S4) of heating the resultant structure, which includes the substrate, and the chips fitted onto the substrate.

Abstract translation: [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US20130252399A1

公开(公告)日：2013-09-26

申请号：US13784001

申请日：2013-03-04

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Patrick LEDUC

IPC: H01L21/02

CPC classification number: H01L21/0226 ,  H01L21/187 ,  H01L23/293 ,  H01L24/05 ,  H01L24/80 ,  H01L2221/1047 ,  H01L2224/05186 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08147 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A method for direct bonding between a first element and a second element, including at least the following steps: deposition of at least one first porous layer on at least one face of the first element, where the first porous layer is compressible, production of at least one bonding layer on the first porous layer, rigid connection by direct bonding of the second element with the first bonding layer.

Abstract translation: 一种用于在第一元件和第二元件之间直接结合的方法，至少包括以下步骤：在第一元件的至少一个表面上沉积至少一个第一多孔层，其中第一多孔层是可压缩的， 在第一多孔层上的至少一个结合层，通过第二元件与第一粘结层的直接接合来进行刚性连接。

公开(公告)号：US20120252162A1

公开(公告)日：2012-10-04

申请号：US13076840

申请日：2011-03-31

Applicant: Mariam Sadaka ,  Ionut Radu ,  Didier Landru ,  Lea Di Cioccio

Inventor： Mariam Sadaka ,  Ionut Radu ,  Didier Landru ,  Lea Di Cioccio

IPC: H01L21/50

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0384 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/8001 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81948 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 将半导体结构结合在一起的方法包括退火第一半导体结构上的第一金属特征，将第一金属特征结合到第二半导体结构的第二金属特征，以形成包含第一金属特征和第二金属特征 ，并对结合的金属结构进行退火。 退火第一金属特征可以包括使第一金属特征经受预结合热预算，并且对接合的金属结构进行退火可以包括使结合的金属结构经受低于预粘合热预算的后粘合热预算 。 使用这种方法制造粘合的半导体结构。

公开(公告)号：US20120032320A1

公开(公告)日：2012-02-09

申请号：US12900016

申请日：2010-10-07

Applicant: TZU-YUAN CHAO ,  CHIA-WEI LIANG ,  YU-TING CHENG

Inventor： TZU-YUAN CHAO ,  CHIA-WEI LIANG ,  YU-TING CHENG

IPC: H01L23/12 ,  H01L21/302 ,  H01L21/50

CPC classification number: H01L23/52 ,  H01L21/02068 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/4985 ,  H01L23/5222 ,  H01L23/66 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/95 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/6627 ,  H01L2224/05005 ,  H01L2224/05155 ,  H01L2224/05541 ,  H01L2224/05644 ,  H01L2224/08238 ,  H01L2224/80006 ,  H01L2224/8001 ,  H01L2224/80203 ,  H01L2224/80444 ,  H01L2224/80895 ,  H01L2224/95 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2924/00

Abstract: A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems.

Abstract translation: 一种用于将芯片集成到柔性基板上以形成柔性微系统的制造方法。 该方法包括低温​​倒装芯片和晶片级制造工艺。 使用低温倒装芯片技术，将芯片金属结合到柔性基板上。 为了将柔性基板与基板分离，使用蚀刻去除柔性基板下方的牺牲层。 本公开使用用于将芯片集成到柔性基板上的标准化微制造工艺。 本发明不使用特殊材料或制造工艺，为柔性微系统提供了具有成本效益的制造方法。

公开(公告)号：US20240234215A9

公开(公告)日：2024-07-11

申请号：US18139674

申请日：2023-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donggap SHIN ,  Yongin LEE ,  Wooyoung KIM ,  Bumki MOON ,  Jiwon MOON ,  Seungdae SEOK ,  Siwoong WOO ,  Byeongtak PARK

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/12 ,  H01L24/74 ,  H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/8001 ,  H01L2224/80894 ,  H01L2224/80908 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/401

Abstract: An apparatus for measuring an adhesion force, the apparatus comprising a stage configured to support a specimen, and a sensor adhered to the specimen, wherein the sensor detects the adhesion force of the specimen, the adhesion force of the specimen being a force for detaching the sensor from the specimen.

公开(公告)号：US20230389339A1

公开(公告)日：2023-11-30

申请号：US18169839

申请日：2023-02-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Chao LIN

IPC: H10B80/00 ,  H01L23/00

CPC classification number: H10B80/00 ,  H01L24/02 ,  H01L24/80 ,  H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05181 ,  H01L2224/05169 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/05571 ,  H01L2224/80357 ,  H01L2224/8001 ,  H01L2224/80895 ,  H01L2224/06158 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor structure includes a first semiconductor layer and a second semiconductor layer bonded to each other. The first semiconductor layer includes a first redistribution line, and the first redistribution line has a first projection length on a bonding surface of the first semiconductor layer and the second semiconductor layer. The second semiconductor layer includes a second redistribution line, and the second redistribution line has a second projection length on the bonding surface. The first projection length is different from the second projection length. The first redistribution line is electrically connected to the second redistribution line. A method for forming the same is also provided.

公开(公告)号：US20180130691A1

公开(公告)日：2018-05-10

申请号：US15629460

申请日：2017-06-21

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/683 ,  H01L21/67 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/6835 ,  H01L21/67092 ,  H01L21/67144 ,  H01L24/75 ,  H01L24/80 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68313 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/08145 ,  H01L2224/7501 ,  H01L2224/753 ,  H01L2224/7565 ,  H01L2224/75755 ,  H01L2224/75804 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/8001 ,  H01L2224/80896 ,  H01L2224/9511 ,  H01L2224/95136 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2224/80001

Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both topside processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that topsides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.