公开(公告)号：US10777651B2

公开(公告)日：2020-09-15

申请号：US16201624

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Yushi Hu ,  John Mark Meldrim ,  Eric Blomiley ,  Everett Allen McTeer ,  Matthew J. King

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

公开(公告)号：US20200006351A1

公开(公告)日：2020-01-02

申请号：US16564896

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Eric Blomiley

IPC: H01L27/108 ,  H01L29/49 ,  C23C16/06 ,  C23C16/455 ,  H01L21/28 ,  H01L21/768 ,  H01L21/285

Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

公开(公告)号：US10164044B2

公开(公告)日：2018-12-25

申请号：US14688387

申请日：2015-04-16

Applicant: Micron Technology, Inc.

Inventor： Yushi Hu ,  John Mark Meldrim ,  Eric Blomiley ,  Everett Allen McTeer ,  Matthew J. King

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

公开(公告)号：US10991701B2

公开(公告)日：2021-04-27

申请号：US16564896

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Eric Blomiley

IPC: H01L27/108 ,  H01L29/49 ,  H01L21/768 ,  C23C16/06 ,  C23C16/455 ,  H01L21/28 ,  H01L21/285 ,  C23C16/04 ,  C23C16/18

Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

公开(公告)号：US10411017B2

公开(公告)日：2019-09-10

申请号：US15692779

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Eric Blomiley ,  Fatma Arzum Simsek-Ege

IPC: H01L21/28 ,  C23C16/06 ,  H01L27/108 ,  H01L29/49 ,  C23C16/455 ,  H01L21/768 ,  H01L21/285

Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

公开(公告)号：US20190067295A1

公开(公告)日：2019-02-28

申请号：US15692779

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Eric Blomiley

IPC: H01L27/108 ,  H01L29/49 ,  H01L21/28 ,  C23C16/455 ,  C23C16/06

CPC classification number: H01L27/10891 ,  C23C16/06 ,  C23C16/45527 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/76846 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966

Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

公开(公告)号：US20160308018A1

公开(公告)日：2016-10-20

申请号：US14688387

申请日：2015-04-16

Applicant: Micron Technology, Inc.

Inventor： Yushi Hu ,  John Mark Meldrim ,  Eric Blomiley ,  Everett Allen McTeer ,  Matthew J. King

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/4933 ,  H01L21/28061 ,  H01L21/28097 ,  H01L29/0649 ,  H01L29/4975 ,  H01L29/66477 ,  H01L29/78

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

Abstract translation: 一些实施例公开了在栅极和STI之间的浅沟槽隔离（STI），硅化钨（WSix）材料之间水平地具有栅极（例如，多晶硅（多晶）材料）的栅极堆叠以及氮化钨（WSiN）材料 在WSix材料的顶面。 一些实施例公开了一种栅极堆叠，其具有在STI之间的栅极，栅极上的第一WSix材料和STI，在第一WSix材料的顶表面上的WSiN夹层材料，以及在WSiN中间层的顶表面上的第二WSix材料 材料。 公开了其他实施例。

公开(公告)号：US20150044860A1

公开(公告)日：2015-02-12

申请号：US14524631

申请日：2014-10-27

Applicant: Micron Technology, Inc.

Inventor： Anurag Jindal ,  Gowri Damarla ,  Roger W. Lindsay ,  Eric Blomiley

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L29/40114 ,  H01L21/02057 ,  H01L21/32134 ,  H01L27/11556

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract translation: 描述形成多层半导体器件的方法以及包括它们的器件。 在一种这样的方法中，硅化物形成在硅层中，硅化物被去除，并且器件至少部分地形成在被硅化物占据的空隙中。 一种这样的设备包括一层硅，在介电材料层之间具有空隙。 残余硅化物位于硅层和/或介电材料层上，并且至少部分地在空隙中形成器件。 还描述了另外的实施例。