公开(公告)号：US20130187212A1

公开(公告)日：2013-07-25

申请号：US13777890

申请日：2013-02-26

Applicant: Micron Technology, Inc.

Inventor： Jonathan Doebler

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L21/76816 ,  H01L28/90

Abstract: Devices having hybrid-vertical contacts. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

Abstract translation: 具有混合垂直触点的装置。 在某些实施例中，衬底包括具有靶导体的下图案层。 混合垂直接触件可以直接设置在目标导体上。 混合垂直触点可以包括直接在目标导体上的下垂直触点和直接在下垂直触点上的上垂直触点。 上垂直接触件可以具有大于下垂直接触件的较低宽度的上宽度。

公开(公告)号：US20130069220A1

公开(公告)日：2013-03-21

申请号：US13674254

申请日：2012-11-12

Applicant: Micron Technology, Inc.

Inventor： Jonathan Doebler

IPC: H01L23/48

CPC classification number: H01L27/10814 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.

Abstract translation: 本发明一般涉及一种形成存储器件的触点的方法。 在一个说明性实施例中，该方法包括在双位存储器单元的有效区域上方形成绝缘材料层，在绝缘材料层之上形成硬掩模层，硬掩模层具有原始厚度，执行至少两个 在硬掩模层上部分蚀刻工艺，从而在绝缘材料层之上限定图案化的硬掩模层，其中每个部分蚀刻工艺被设计成蚀刻穿过小于硬掩模层的原始厚度，硬掩模层 具有形成在其中的开口对应于双位存储单元的数字线触点和多个存储节点触点，并且执行至少一个蚀刻工艺以在数字线触点和多个存储节点的绝缘材料层中形成开口 使用图案化的硬掩模层作为蚀刻掩模的触点。

公开(公告)号：US09337053B2

公开(公告)日：2016-05-10

申请号：US13674254

申请日：2012-11-12

Applicant: Micron Technology, Inc.

Inventor： Jonathan Doebler

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L27/10814 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.

Abstract translation: 本发明一般涉及一种形成存储器件的触点的方法。 在一个说明性实施例中，该方法包括在双位存储器单元的有效区域上方形成绝缘材料层，在绝缘材料层之上形成硬掩模层，硬掩模层具有原始厚度，执行至少两个 在硬掩模层上部分蚀刻工艺，从而在绝缘材料层之上限定图案化的硬掩模层，其中每个部分蚀刻工艺被设计成蚀刻穿过小于硬掩模层的原始厚度，硬掩模层 具有形成在其中的开口对应于双位存储单元的数字线触点和多个存储节点触点，并且执行至少一个蚀刻工艺以在数字线触点和多个存储节点的绝缘材料层中形成开口 使用图案化的硬掩模层作为蚀刻掩模的触点。

公开(公告)号：US08884351B2

公开(公告)日：2014-11-11

申请号：US13777890

申请日：2013-02-26

Applicant: Micron Technology, Inc.

Inventor： Jonathan Doebler

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L28/92 ,  H01L21/76816 ,  H01L28/90

Abstract: Devices having hybrid-vertical contacts. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

Abstract translation: 具有混合垂直触点的装置。 在某些实施例中，衬底包括具有靶导体的下图案层。 混合垂直接触件可以直接设置在目标导体上。 混合垂直触点可以包括直接在目标导体上的下垂直触点和直接在下垂直触点上的上垂直触点。 上垂直接触件可以具有大于下垂直接触件的较低宽度的上宽度。

公开(公告)号：US20150036442A1

公开(公告)日：2015-02-05

申请号：US13957273

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard Kirsch ,  Charles Ingalls ,  K. Shawn Smith ,  Jonathan Doebler

IPC: G11C7/12

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/418

Abstract: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.

Abstract translation: 描述了设备，全局和本地字线驱动器以及用于驱动存储器中字线电压的方法。 示例性装置包括包括多个子阵列的存储器阵列。 多个子阵列耦合到字线。 存储器阵列还包括耦合在全局字线和字线之间的多个本地字线驱动器。 多个本地字线驱动器被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。 该示例设备还包括全局字线驱动器，其被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。

公开(公告)号：US09147473B2

公开(公告)日：2015-09-29

申请号：US13957273

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard Kirsch ,  Charles Ingalls ,  K. Shawn Smith ,  Jonathan Doebler

IPC: G11C16/08 ,  G11C8/08 ,  G11C11/408 ,  G11C11/418 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/418

Abstract: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.

Abstract translation: 描述了设备，全局和本地字线驱动器以及用于驱动存储器中字线电压的方法。 示例性装置包括包括多个子阵列的存储器阵列。 多个子阵列耦合到字线。 存储器阵列还包括耦合在全局字线和字线之间的多个本地字线驱动器。 多个本地字线驱动器被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。 该示例设备还包括全局字线驱动器，其被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。