公开(公告)号：US20160217834A1

公开(公告)日：2016-07-28

申请号：US15091459

申请日：2016-04-05

Applicant: Micron Technology, Inc.

Inventor： Tae Kim

IPC: G11C7/08 ,  G11C5/14

CPC classification number: G11C7/08 ,  G11C5/148 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract translation: 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在Psense放大器控制线（例如ACT）和Vcc之间和/或在Nsense放大器控制线（例如RNL *）和Vss（地电位）之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能，但在有功掉电模式下导通，以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可以在掉电模式下降低ACT线路上的电压，而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压，以降低读出放大器的漏电流 通过这些节点。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US09336837B2

公开(公告)日：2016-05-10

申请号：US14172620

申请日：2014-02-04

Applicant: Micron Technology, Inc.

Inventor： Tae Kim

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091

CPC classification number: G11C7/08 ,  G11C5/148 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract translation: 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在Psense放大器控制线（例如ACT）和Vcc之间和/或在Nsense放大器控制线（例如RNL *）和Vss（地电位）之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能，但在有功掉电模式下导通，以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可能会在掉电模式下降低ACT线路上的电压，而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压，以降低读出放大器的漏电流 通过这些节点。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US20150036442A1

公开(公告)日：2015-02-05

申请号：US13957273

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard Kirsch ,  Charles Ingalls ,  K. Shawn Smith ,  Jonathan Doebler

IPC: G11C7/12

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/418

Abstract: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.

Abstract translation: 描述了设备，全局和本地字线驱动器以及用于驱动存储器中字线电压的方法。 示例性装置包括包括多个子阵列的存储器阵列。 多个子阵列耦合到字线。 存储器阵列还包括耦合在全局字线和字线之间的多个本地字线驱动器。 多个本地字线驱动器被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。 该示例设备还包括全局字线驱动器，其被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。

公开(公告)号：US20140226427A1

公开(公告)日：2014-08-14

申请号：US14254433

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

Abstract: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

Abstract translation: 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个局部字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US09449657B2

公开(公告)日：2016-09-20

申请号：US15091459

申请日：2016-04-05

Applicant: Micron Technology, Inc.

Inventor： Tae Kim

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C5/148 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A damping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The damping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract translation: 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在Psense放大器控制线（例如ACT）和Vcc之间和/或Nsense放大器控制线（例如RNL *）和Vss（地电位）之间使用阻尼器件或二极管。 钳位二极管在正常存储器操作期间不使能，但在有功掉电模式下导通，以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的阻尼装置可以在掉电模式下降低ACT线上的电压，而连接到RNL *节点的钳位装置可以在掉电模式期间增加RNL *线上的电压，以减少读出放大器的漏电流 通过这些节点。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US09159392B2

公开(公告)日：2015-10-13

申请号：US14254433

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC: G11C5/02 ,  G11C8/08 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  G11C8/14 ,  H01L27/118

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

Abstract: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

Abstract translation: 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US09147473B2

公开(公告)日：2015-09-29

申请号：US13957273

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard Kirsch ,  Charles Ingalls ,  K. Shawn Smith ,  Jonathan Doebler

IPC: G11C16/08 ,  G11C8/08 ,  G11C11/408 ,  G11C11/418 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/418

Abstract: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.

Abstract translation: 描述了设备，全局和本地字线驱动器以及用于驱动存储器中字线电压的方法。 示例性装置包括包括多个子阵列的存储器阵列。 多个子阵列耦合到字线。 存储器阵列还包括耦合在全局字线和字线之间的多个本地字线驱动器。 多个本地字线驱动器被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。 该示例设备还包括全局字线驱动器，其被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。

公开(公告)号：US20140153343A1

公开(公告)日：2014-06-05

申请号：US14172620

申请日：2014-02-04

Applicant: Micron Technology, Inc.

Inventor： Tae Kim

IPC: G11C7/08

CPC classification number: G11C7/08 ,  G11C5/148 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract translation: 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在Psense放大器控制线（例如ACT）和Vcc之间和/或在Nsense放大器控制线（例如RNL *）和Vss（地电位）之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能，但在有功掉电模式下导通，以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可以在掉电模式下降低ACT线路上的电压，而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压，以降低读出放大器的漏电流 通过这些节点。 由于管理摘要的规则，本摘要不应用于解释索赔。