公开(公告)号：US11783896B2

公开(公告)日：2023-10-10

申请号：US17401239

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/14 ,  G11C16/08 ,  H01L29/78 ,  H01L29/10 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H01L29/1083 ,  H01L29/7833

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

公开(公告)号：US12112804B2

公开(公告)日：2024-10-08

申请号：US18237070

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H01L29/1083 ,  H01L29/7833

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

公开(公告)号：US20230050443A1

公开(公告)日：2023-02-16

申请号：US17401239

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/08 ,  G11C16/04 ,  H01L29/10 ,  H01L29/78

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

公开(公告)号：US20250022882A1

公开(公告)日：2025-01-16

申请号：US18768932

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Martin W. Popp ,  Zia A. Shafi

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

Abstract: A semiconductor device including a complementary metal-oxide-semiconductor (CMOS) device that includes a P-Well region including a P-Well, a first shallow trench isolation (STI) region that is disposed on a frontside surface of the CMOS device and above the P-Well, and a first deep trench isolation (DTI) region that is disposed under the first STI region and that extends to a backside surface of the CMOS device, the first DTI region completely surrounding the P-Well, and a N-Well region adjacent to the P-Well region, the N-Well region including a N-Well, a second STI region disposed on the frontside surface of the CMOS device and above the N-Well, and a second DTI region that is disposed under the second STI region and that extends to the backside of the CMOS device, the second DTI region completely surrounding the N-Well; and a secondary device bonded to the CMOS device.

公开(公告)号：US20240428859A1

公开(公告)日：2024-12-26

申请号：US18830525

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/08 ,  G11C16/04 ,  H01L29/10 ,  H01L29/78

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

公开(公告)号：US20240290385A1

公开(公告)日：2024-08-29

申请号：US18409702

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Shyam Surthi ,  Martin W. Popp ,  KangYoul Lee ,  Yui Shimizu

IPC: G11C16/04 ,  H01L23/528

CPC classification number: G11C16/0483 ,  H01L23/5283

Abstract: A microelectronic device comprises, a control circuitry structure comprising an active region including control logic circuitry at least partially within a semiconductive material; a bond pad on a backside of the control circuitry structure; a conductive contact vertically extending from the bond pad, through the semiconductive material, and to the control logic circuitry; and a dielectric-filled slit vertically extending into the semiconductive material and horizontally circumscribing the conductive contact, portions of the semiconductive material horizontally interposed between the conductive contact and the dielectric-filled slit. Additional microelectronic devices, memory devices, microelectronic device packages, and electronic systems are also described.

公开(公告)号：US20240274533A1

公开(公告)日：2024-08-15

申请号：US18416227

申请日：2024-01-18

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp ,  Richard J. Hill

IPC: H01L23/528 ,  G11C5/06 ,  G11C16/04 ,  H01L21/762 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L23/5283 ,  G11C5/063 ,  G11C16/0483 ,  H01L21/76224 ,  H01L25/0657 ,  H01L27/0922 ,  H01L29/0649 ,  H01L2225/06524

Abstract: A semiconductor device assembly including a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines being connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding string driver, wherein a backside surface of the first wafer is bonded to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding.

公开(公告)号：US20230395151A1

公开(公告)日：2023-12-07

申请号：US18237070

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/08 ,  H01L29/78 ,  H01L29/10 ,  G11C16/04

CPC classification number: G11C16/08 ,  H01L29/7833 ,  H01L29/1083 ,  G11C16/0483

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.